clk: introduce TC9564 clock support
v2 cover clk: introduce TC9564 clock support
This series adds support for the clock controller present within the Toshiba TC9564 SoC.
This SoC attaches to a host system via PCIe. It includes a PCIe switch with three downstream ports. To one of these ports an embedded PCIe endpoint is attached, and it implements two PCI functions. BAR 4 for both PCI functions provides access to the registers that enable or disable a set of clocks.
Both TC9564 PCI functions provide PCI endpoint buses via devicetree. Each PCI endpoint bus provides access to one of the function's BARs. Subordinate devices (like the clock controller) can then be defined as nodes accessible on the endpoint bus.
Only one of the two PCI functions is permitted to define the clock device node.
-Alex
NOTE:
This series is built upon linux-next, with this patch applied:
https://lore.kernel.org/lkml/[email protected]/
It is available in this git branch:
https://github.com/alexelder/linux/tree/outgoing/clock-v2
Between version 1 and version 2:
- Previously, this driver also included reset functionality. That is now in a separate reset (only) driver, which will be sent for review separately
- Dropped the "config syscon" devicetree binding
- Reworded the clock binding description to focus on hardware only
- Clock IDs are now consecutive (no more commented-out values)
- Get the definition of of_device_id from <linux/device_id/of.h> rather than <linux/platform_device.h>
- Dropped a comma that followed a ternminating empty array entry
- Config option COMMON_CLK_TC9564 now selects MFD_SYSCON
- Clarified in config help text that the reset and stmmac drivers are the "others" that use the config syscon
- Moved the clock devicetree node to be a peer (rather than a child) of the syscon node.
Version 1 is available here:
https://lore.kernel.org/lkml/[email protected]/
Alex Elder (3):
dt-bindings: clock: introduce toshiba,tc9564-clock.yaml
clk: toshiba: introduce a TC9564 SoC clock driver
arm64: dts: qcom: qcs6490-rb3gen2: add the clock controller
.../bindings/clock/toshiba,tc9564-clock.yaml | 54 ++++ MAINTAINERS | 8 + arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 16 +- drivers/clk/Kconfig | 12 + drivers/clk/Makefile | 1 + drivers/clk/clk-tc9564.c | 262 ++++++++++++++++++ include/dt-bindings/clock/toshiba,tc9564.h | 34 +++ 7 files changed, 386 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml create mode 100644 drivers/clk/clk-tc9564.c create mode 100644 include/dt-bindings/clock/toshiba,tc9564.h
base-commit: e8e67c48ac5cd9b0e7ba4ba2cef9decfa7327833
Signature · 1 line
2.53.0
PATCH v2 1/3 dt-bindings: clock: introduce toshiba,tc9564-clock.yaml
Define the binding for the clock controller functionality present in the Toshiba TC9564 SoC.
---
v2: - Only define clock information, not reset information
- Reworded description to avoid talking about software
- Clock IDs are now consecutive (no more commented-out values)
.../bindings/clock/toshiba,tc9564-clock.yaml | 54 +++++++++++++++++++ MAINTAINERS | 7 +++ include/dt-bindings/clock/toshiba,tc9564.h | 34 ++++++++++++ 3 files changed, 95 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml create mode 100644 include/dt-bindings/clock/toshiba,tc9564.h
Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml new file +54 -0
@@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/toshiba,tc9564-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba TC9564 Clock Controller + +maintainers: + - Alex Elder <[email protected]> + - Daniel Thompson <[email protected]> + +description: + The Toshiba TC9564 is an SoC accessed by a host system through the + upstream PCIe port on the PCIe switch it implements. The switch + includes an embedded PCIe endpoint that provides access to various + SoC peripherals (including a clock controller) via its BARs. + + A total of 21 clocks are implemented, though two of these are not + controllable. Access to the clock controller relies on PCIe being + functional, so the PCIe clock is assumed to be always on. Similarly, + the PCIe controller relies on I2C, so the I2C clock is also assumed + to be always on. + + Clock ids are defined in <dt-bindings/clock/toshiba,tc9564.h>. + +properties: + compatible: + const: toshiba,tc9564-clock + + toshiba,config-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle for the configuration space system controller. + + "#clock-cells": + const: 1 + +required: + - compatible + - toshiba,config-syscon + - "#clock-cells" + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/toshiba,tc9564.h> + + clock { + compatible = "toshiba,tc9564-clock"; + toshiba,config-syscon = <&tc9564_config_syscon0>; + #clock-cells = <1>; + };
MAINTAINERS +7 -0
@@ -28128,6 +28128,13 @@ F: Documentation/devicetree/bindings/media/i2c/toshiba,tc358743.yaml F: drivers/media/i2c/tc358743* F: include/media/i2c/tc358743.h +TOSHIBA TC9564 CLOCK DRIVER +M: Alex Elder <[email protected]> +M: Daniel Thompson <[email protected]> +S: Maintained +F: Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml +F: include/dt-bindings/clock/toshiba,tc9564.h + TOSHIBA TC9564 PCI DRIVER M: Alex Elder <[email protected]> M: Daniel Thompson <[email protected]>
include/dt-bindings/clock/toshiba,tc9564.h new file +34 -0
@@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +/* +* Copyright (C) 2026 by RISCstar Solutions Corporation. All rights reserved. +*/ + +#ifndef __CLOCK_TOSHIBA_TC9564_H__ +#define __CLOCK_TOSHIBA_TC9564_H__ + +/* Clock IDs */ + +#define CLOCK_MCU 0 +#define CLOCK_INTC 1 +#define CLOCK_SRAM 2 +#define CLOCK_UART 3 +#define CLOCK_MSIGEN 4 +#define CLOCK_PLL 5 +#define CLOCK_SGMII 6 +#define CLOCK_REFCLKO 7 + +#define CLOCK_MAC0_TX 8 +#define CLOCK_MAC0_RX 9 +#define CLOCK_MAC0_125M 10 +#define CLOCK_MAC0_312_5M 11 +#define CLOCK_MAC0_ALL 12 + +#define CLOCK_MAC1_TX 13 +#define CLOCK_MAC1_RX 14 +#define CLOCK_MAC1_RMII 15 +#define CLOCK_MAC1_125M 16 +#define CLOCK_MAC1_312_5M 17 +#define CLOCK_MAC1_ALL 18 + +#endif /* __CLOCK_TOSHIBA_TC9564_H__*/
Signature · 1 line
2.53.0
Re: [PATCH v2 1/3] dt-bindings: clock: introduce toshiba,tc9564-clock.yaml
Quoted 48 lines · Alex Elder
Define the binding for the clock controller functionality present in the Toshiba TC9564 SoC.
Co-developed-by Daniel Thompson <[email protected]>Signed-off-by Daniel Thompson <[email protected]>Signed-off-by Alex Elder <[email protected]>---
v2: - Only define clock information, not reset information
- Reworded description to avoid talking about software
- Clock IDs are now consecutive (no more commented-out values).../bindings/clock/toshiba,tc9564-clock.yaml | 54 +++++++++++++++++++ MAINTAINERS | 7 +++ include/dt-bindings/clock/toshiba,tc9564.h | 34 ++++++++++++ 3 files changed, 95 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml create mode 100644 include/dt-bindings/clock/toshiba,tc9564.hDocumentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml new file +24
-0@@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/toshiba,tc9564-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba TC9564 Clock Controller + +maintainers: + - Alex Elder <[email protected]> + - Daniel Thompson <[email protected]> + +description: + The Toshiba TC9564 is an SoC accessed by a host system through the + upstream PCIe port on the PCIe switch it implements. The switch + includes an embedded PCIe endpoint that provides access to various + SoC peripherals (including a clock controller) via its BARs. + + A total of 21 clocks are implemented, though two of these are not + controllable. Access to the clock controller relies on PCIe being + functional, so the PCIe clock is assumed to be always on. Similarly, + the PCIe controller relies on I2C, so the I2C clock is also assumed + to be always on. +
Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml line 34
Quoted 10 lines
Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml new file +10
-0+ Clock ids are defined in <dt-bindings/clock/toshiba,tc9564.h>. + +properties: + compatible: + const: toshiba,tc9564-clock + + toshiba,config-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle for the configuration space system controller.
I do not see my previous comment addressed - you have no resources here, so this belongs to the parent. You responded something about pci-ep, but the parent is not pci-ep. Open your code:
https://lore.kernel.org/lkml/[email protected]/
I clearly see code like:
syscon {
clock@ {
};};
so I do not understand what pci-ep has anything to do here.
What's more, I still do not see any usage of these clocks outside. And I still did not receive actual answers (or I missed them) how these clocks are routed OUTSIDE of the connector. You said for example:
"Ultimately the TC9564 SoC has a single 25 MHz input clock,"
but that is input. I did not ask how this device receives clocks. I asked how the host receives the clocks from this device.
Quoted 4 lines
Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml new file +4
-0+ + "#clock-cells": + const: 1 +
Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml line 48
Quoted 10 lines
Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml new file +10
-0+required: + - compatible + - toshiba,config-syscon + - "#clock-cells" + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/toshiba,tc9564.h>
Looks unused.
Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml line 50
Quoted 2 lines
Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml new file +2
-0+ + clock {
Anyway, if this stays, that's a clock-controller.
Best regards,
Krzysztof
Re: [PATCH v2 1/3] dt-bindings: clock: introduce toshiba,tc9564-clock.yaml
Quoted 7 lines · Krzysztof Kozlowski
Quoted 6 lines · Alex Elder
Define the binding for the clock controller functionality present in the Toshiba TC9564 SoC.
Co-developed-by Daniel Thompson <[email protected]>Signed-off-by Daniel Thompson <[email protected]>Signed-off-by Alex Elder <[email protected]>
I'm just about to send version 3 of this series (and then a new reset series derived from the code that was previously combined with the clock code). Some things related to what you mention have changed. I show that below, but also respond to your other comments, and try to advocate for the approach used.
Quoted 58 lines
Quoted 42 lines
---
v2: - Only define clock information, not reset information
- Reworded description to avoid talking about software
- Clock IDs are now consecutive (no more commented-out values).../bindings/clock/toshiba,tc9564-clock.yaml | 54 +++++++++++++++++++ MAINTAINERS | 7 +++ include/dt-bindings/clock/toshiba,tc9564.h | 34 ++++++++++++ 3 files changed, 95 insertions(+)create mode 100644
Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yamlcreate mode 100644include/dt-bindings/clock/toshiba,tc9564.hDocumentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml new file +24
-0@@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/toshiba,tc9564-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba TC9564 Clock Controller + +maintainers: + - Alex Elder <[email protected]> + - Daniel Thompson <[email protected]> + +description: + The Toshiba TC9564 is an SoC accessed by a host system through the + upstream PCIe port on the PCIe switch it implements. The switch + includes an embedded PCIe endpoint that provides access to various + SoC peripherals (including a clock controller) via its BARs. + + A total of 21 clocks are implemented, though two of these are not + controllable. Access to the clock controller relies on PCIe being + functional, so the PCIe clock is assumed to be always on. Similarly, + the PCIe controller relies on I2C, so the I2C clock is also assumed + to be always on. +Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml line 34
Quoted 10 lines
Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml new file +10
-0+ Clock ids are defined in <dt-bindings/clock/toshiba,tc9564.h>. + +properties: + compatible: + const: toshiba,tc9564-clock + + toshiba,config-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle for the configuration space system controller.I do not see my previous comment addressed - you have no resources here, so this belongs to the parent. You responded something about pci-ep, but the parent is not pci-ep. Open your code:
https://lore.kernel.org/lkml/[email protected]/
Quoted 7 lines
I clearly see code like:
syscon { clock@ { }; };so I do not understand what pci-ep has anything to do here.
What I have now (about to send) looks like this:
syscon@0 {
compatible = "syscon", "simple-mfd";
reg = <0x0 0x2000>;
clock {
compatible = "toshiba,tc9564-clock";
#clock-cells = <1>;
};
};A reset node will also go inside the syscon, so there is another function for that MFD.
The regmap belongs to the parent, and is looked up this way:
regmap = syscon_node_to_regmap(dev_of_node(dev->parent));
Quoted 7 lines
What's more, I still do not see any usage of these clocks outside. And I still did not receive actual answers (or I missed them) how these clocks are routed OUTSIDE of the connector. You said for example:
"Ultimately the TC9564 SoC has a single 25 MHz input clock,"but that is input. I did not ask how this device receives clocks. I asked how the host receives the clocks from this device.
I was explaining that the clock input gets split into a number of "output" clocks derived from that one input. However you're right, almost all of these clocks are connected to blocks internal to the SoC. There is only one 25 MHz clock that is exposed externally (CLOCK_REFCLKO).
I think your point (or one of them) is that, even if pci-ep-bus is used, the only things that warrant being described with devicetree are those that can affect things outside the chip. Everything else is not really variable from the perspective of the platform, and inner details can be determined (and controlled) by software.
Our original version of this code incorporated clock and reset control inside the networking driver. Rob commented that the DWMAC driver should bind to the PCI functions and "everything else...should be under the PCIe switch upstream node in a pci-ep.bus".
The only driver associated with the switch inside the TC9564 is the special power control driver, accessed via I2C. The PCI switch functionality is otherwise provided without any special handling, or is handled by generic code.
What *is* available is the PCI endpoint functions and their BARs, so the endpoint buses use those.
PCI endpoint bus makes available things that devicetree does that are very useful (including a standard way of describing connections between blocks in the SoC).
I know that doesn't address the "exposed clocks" issue, but it provides some background on why things were done the way they were.
The single exposed clock *might* justify presenting the clock controller device in devicetree. There are also resets exposed externally via GPIOs, and these control external entities (PHYs).
But I'll reiterate how *nice* it is to use devicetree to model the inner structure and of this SoC and the connections between its various parts. The DWMAC device driver can use standard Linux clock (and reset, etc.) interfaces to manage them--as if they were provided externally, or as if they *could* be provided by something outside the TC9564.
There was no need to implement "unrelated" clock driver code inside the DWMAC driver. Granted, enabling/disabling the clocks amounts to trivial register updates. But supporting two separate PCI functions that share access to those clocks requires adding reference counting logic for every clock, and it's just a lot nicer to benefit from the core Linux code that already does that very well.
This is part of why I asked about the use of devicetree overlays. Can devicetree be used to describe an SoC (as if it were an attached board)? Would separating the DTS portion into an overlay make this more palatable?
(Is this what the RPi RP1 does?)
Quoted 8 lines
Quoted 8 lines
Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml new file +8
-0+ + "#clock-cells": + const: 1 + +required: + - compatible + - toshiba,config-syscon + - "#clock-cells"
Quoted 8 lines
Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml line 48
Quoted 6 lines
Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml new file +6
-0+ +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/toshiba,tc9564.h>Looks unused.
You're right, it's unused in the example. I'll remove this.
Quoted 5 lines
Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml line 50
Quoted 3 lines
Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml new file +2
-0+ + clock {Anyway, if this stays, that's a clock-controller.
OK. I'm still going to send version 3 shortly.
-Alex
Quoted 3 lines
Best regards,
Krzysztof
Re: [PATCH v2 1/3] dt-bindings: clock: introduce toshiba,tc9564-clock.yaml
Quoted 93 lines · Alex Elder
Quoted 7 lines · Krzysztof Kozlowski
Quoted 6 lines · Alex Elder
Define the binding for the clock controller functionality present in the Toshiba TC9564 SoC.
Co-developed-by Daniel Thompson <[email protected]>Signed-off-by Daniel Thompson <[email protected]>Signed-off-by Alex Elder <[email protected]>I'm just about to send version 3 of this series (and then a new reset series derived from the code that was previously combined with the clock code). Some things related to what you mention have changed. I show that below, but also respond to your other comments, and try to advocate for the approach used.
Quoted 58 lines
Quoted 42 lines
---
v2: - Only define clock information, not reset information
- Reworded description to avoid talking about software
- Clock IDs are now consecutive (no more commented-out values).../bindings/clock/toshiba,tc9564-clock.yaml | 54 +++++++++++++++++++ MAINTAINERS | 7 +++ include/dt-bindings/clock/toshiba,tc9564.h | 34 ++++++++++++ 3 files changed, 95 insertions(+)create mode 100644
Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yamlcreate mode 100644include/dt-bindings/clock/toshiba,tc9564.hDocumentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml new file +24
-0@@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/toshiba,tc9564-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba TC9564 Clock Controller + +maintainers: + - Alex Elder <[email protected]> + - Daniel Thompson <[email protected]> + +description: + The Toshiba TC9564 is an SoC accessed by a host system through the + upstream PCIe port on the PCIe switch it implements. The switch + includes an embedded PCIe endpoint that provides access to various + SoC peripherals (including a clock controller) via its BARs. + + A total of 21 clocks are implemented, though two of these are not + controllable. Access to the clock controller relies on PCIe being + functional, so the PCIe clock is assumed to be always on. Similarly, + the PCIe controller relies on I2C, so the I2C clock is also assumed + to be always on. +Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml line 34
Quoted 10 lines
Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml new file +10
-0+ Clock ids are defined in <dt-bindings/clock/toshiba,tc9564.h>. + +properties: + compatible: + const: toshiba,tc9564-clock + + toshiba,config-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle for the configuration space system controller.I do not see my previous comment addressed - you have no resources here, so this belongs to the parent. You responded something about pci-ep, but the parent is not pci-ep. Open your code:
https://lore.kernel.org/lkml/[email protected]/Quoted 7 lines
I clearly see code like:
syscon { clock@ { }; };so I do not understand what pci-ep has anything to do here.
What I have now (about to send) looks like this:
syscon@0 { compatible = "syscon", "simple-mfd"; reg = <0x0 0x2000>; clock { compatible = "toshiba,tc9564-clock"; #clock-cells = <1>; }; };
Quoted 6 lines
A reset node will also go inside the syscon, so there is another function for that MFD.
The regmap belongs to the parent, and is looked up this way:
regmap = syscon_node_to_regmap(dev_of_node(dev->parent));
That's driver code, so irrelevant. So how does this solve my comment from v1?
Quoted 47 lines
Quoted 8 lines
What's more, I still do not see any usage of these clocks outside. And I still did not receive actual answers (or I missed them) how these clocks are routed OUTSIDE of the connector. You said for example:
"Ultimately the TC9564 SoC has a single 25 MHz input clock,"but that is input. I did not ask how this device receives clocks. I asked how the host receives the clocks from this device.
I was explaining that the clock input gets split into a number of "output" clocks derived from that one input. However you're right, almost all of these clocks are connected to blocks internal to the SoC. There is only one 25 MHz clock that is exposed externally (
CLOCK_REFCLKO).I think your point (or one of them) is that, even if pci-ep-bus is used, the only things that warrant being described with devicetree are those that can affect things outside the chip. Everything else is not really variable from the perspective of the platform, and inner details can be determined (and controlled) by software.
Our original version of this code incorporated clock and reset control inside the networking driver. Rob commented that the DWMAC driver should bind to the PCI functions and "everything else...should be under the PCIe switch upstream node in a pci-ep.bus".
The only driver associated with the switch inside the TC9564 is the special power control driver, accessed via I2C. The PCI switch functionality is otherwise provided without any special handling, or is handled by generic code.
What *is* available is the PCI endpoint functions and their BARs, so the endpoint buses use those.
PCI endpoint bus makes available things that devicetree does that are very useful (including a standard way of describing connections between blocks in the SoC).
I know that doesn't address the "exposed clocks" issue, but it provides some background on why things were done the way they were.
Quoted 4 lines
The single exposed clock *might* justify presenting the clock controller device in devicetree. There are also resets exposed externally via GPIOs, and these control external entities (PHYs).
I cannot find any of these exposed. Please point me to DTS code showing this.
Best regards,
Krzysztof
Re: [PATCH v2 1/3] dt-bindings: clock: introduce toshiba,tc9564-clock.yaml
Quoted 9 lines · Krzysztof Kozlowski
Quoted 8 lines · Alex Elder
Quoted 7 lines · Krzysztof Kozlowski
Quoted 6 lines · Alex Elder
Define the binding for the clock controller functionality present in the Toshiba TC9564 SoC.
Co-developed-by Daniel Thompson <[email protected]>Signed-off-by Daniel Thompson <[email protected]>Signed-off-by Alex Elder <[email protected]>
. . .
Quoted 37 lines
Quoted 37 lines
Quoted 14 lines
Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml line 34
Quoted 8 lines
Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml new file +8
-0+properties: + compatible: + const: toshiba,tc9564-clock + + toshiba,config-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle for the configuration space system controller.I do not see my previous comment addressed - you have no resources here, so this belongs to the parent. You responded something about pci-ep, but the parent is not pci-ep. Open your code:
https://lore.kernel.org/lkml/[email protected]/Quoted 7 lines
I clearly see code like:
syscon { clock@ { }; };so I do not understand what pci-ep has anything to do here.
What I have now (about to send) looks like this:
syscon@0 { compatible = "syscon", "simple-mfd"; reg = <0x0 0x2000>; clock { compatible = "toshiba,tc9564-clock"; #clock-cells = <1>; }; };A reset node will also go inside the syscon, so there is another function for that MFD.
Quoted 6 lines
Quoted 3 lines
The regmap belongs to the parent, and is looked up this way:
regmap = syscon_node_to_regmap(dev_of_node(dev->parent));That's driver code, so irrelevant. So how does this solve my comment from v1?
I'm trying Krzysztof.
The clock controller uses two registers, 0x1004 and 0x100c, to manage whether a set of clock signals are enabled or not. (The reset controller uses two adjacent registers, 0x1008 and 0x1010, to manage whether a set of reset signals are asserted or not.)
You said "no resources except a small address space" and I guess it's not clear to me what size is "big enough" to warrant representing something as a separate device.
*One* of the managed clocks is a 25 MHz clock, exposed through a pin on the SoC. That one clock signal is therefore usable by the platform (although on the RB3gen2 it's not used).
Rather than expose the register addresses in the clock node, a syscon is defined, covering 8 KB, and the actual offsets used are just defined in the clock and reset driver source code.
If that's not the right thing to do, please say that.
Quoted 4 lines
Quoted 4 lines
Quoted 4 lines
What's more, I still do not see any usage of these clocks outside. And I still did not receive actual answers (or I missed them) how these clocks are routed OUTSIDE of the connector. You said for example:
"Ultimately the TC9564 SoC has a single 25 MHz input clock,"
. . .
Quoted 7 lines
Quoted 4 lines
The single exposed clock *might* justify presenting the clock controller device in devicetree. There are also resets exposed externally via GPIOs, and these control external entities (PHYs).
I cannot find any of these exposed. Please point me to DTS code showing this.
It is not used by this platform, but is available for other platforms to use. Its name is "REFCLKO" and is exposed on ball C17 of the SoC, if a platform designer decided to use it.
I only mention its existence as a reason to justify defining the clock as a separate device, but I realize you are arguing that I should do it somehow differently.
-Alex
Quoted 3 lines
Best regards,
Krzysztof
Re: [PATCH v2 1/3] dt-bindings: clock: introduce toshiba,tc9564-clock.yaml
Quoted 99 lines · Alex Elder
Quoted 9 lines · Krzysztof Kozlowski
Quoted 8 lines · Alex Elder
Quoted 7 lines · Krzysztof Kozlowski
Quoted 6 lines · Alex Elder
Define the binding for the clock controller functionality present in the Toshiba TC9564 SoC.
Co-developed-by Daniel Thompson <[email protected]>Signed-off-by Daniel Thompson <[email protected]>Signed-off-by Alex Elder <[email protected]>. . .
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Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml line 34
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Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml new file +8
-0+properties: + compatible: + const: toshiba,tc9564-clock + + toshiba,config-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle for the configuration space system controller.I do not see my previous comment addressed - you have no resources here, so this belongs to the parent. You responded something about pci-ep, but the parent is not pci-ep. Open your code:
https://lore.kernel.org/lkml/[email protected]/Quoted 7 lines
I clearly see code like:
syscon { clock@ { }; };so I do not understand what pci-ep has anything to do here.
What I have now (about to send) looks like this:
syscon@0 { compatible = "syscon", "simple-mfd"; reg = <0x0 0x2000>; clock { compatible = "toshiba,tc9564-clock"; #clock-cells = <1>; }; };A reset node will also go inside the syscon, so there is another function for that MFD.
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The regmap belongs to the parent, and is looked up this way:
regmap = syscon_node_to_regmap(dev_of_node(dev->parent));That's driver code, so irrelevant. So how does this solve my comment from v1?
I'm trying Krzysztof.
The clock controller uses two registers,
0x1004and0x100c, to manage whether a set of clock signals are enabled or not. (The reset controller uses two adjacent registers,0x1008and0x1010, to manage whether a set of reset signals are asserted or not.)You said "no resources except a small address space" and I guess it's not clear to me what size is "big enough" to warrant representing something as a separate device.
*One* of the managed clocks is a 25 MHz clock, exposed through a pin on the SoC. That one clock signal is therefore usable by the platform (although on the RB3gen2 it's not used).
Rather than expose the register addresses in the clock node, a syscon is defined, covering 8 KB, and the actual offsets used are just defined in the clock and reset driver source code.
If that's not the right thing to do, please say that.
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What's more, I still do not see any usage of these clocks outside. And I still did not receive actual answers (or I missed them) how these clocks are routed OUTSIDE of the connector. You said for example:
"Ultimately the TC9564 SoC has a single 25 MHz input clock,". . .
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The single exposed clock *might* justify presenting the clock controller device in devicetree. There are also resets exposed externally via GPIOs, and these control external entities (PHYs).
I cannot find any of these exposed. Please point me to DTS code showing this.
It is not used by this platform, but is available for other platforms to use. Its name is "REFCLKO" and is exposed on ball C17 of the SoC, if a platform designer decided to use it.
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I only mention its existence as a reason to justify defining the clock as a separate device, but I realize you are arguing that I should do it somehow differently.
-Alex
While on the topic of description, I'm little bit concerned that this controller does not any input ? Does it have an on-board oscillator somehow ?
None of the clocks described in your driver take a parent from what I can see. It is as if the clocks of this device are generated out of thin air. Is it really how this works ?
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Best regards,
Krzysztof
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Jerome
Re: [PATCH v2 1/3] dt-bindings: clock: introduce toshiba,tc9564-clock.yaml
Quoted 105 lines · Jerome Brunet
Quoted 103 lines · Alex Elder
Quoted 9 lines · Krzysztof Kozlowski
Quoted 8 lines · Alex Elder
Quoted 7 lines · Krzysztof Kozlowski
Quoted 6 lines · Alex Elder
Define the binding for the clock controller functionality present in the Toshiba TC9564 SoC.
Co-developed-by Daniel Thompson <[email protected]>Signed-off-by Daniel Thompson <[email protected]>Signed-off-by Alex Elder <[email protected]>. . .
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Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml line 34
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Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml new file +8
-0+properties: + compatible: + const: toshiba,tc9564-clock + + toshiba,config-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle for the configuration space system controller.I do not see my previous comment addressed - you have no resources here, so this belongs to the parent. You responded something about pci-ep, but the parent is not pci-ep. Open your code:
https://lore.kernel.org/lkml/[email protected]/Quoted 7 lines
I clearly see code like:
syscon { clock@ { }; };so I do not understand what pci-ep has anything to do here.
What I have now (about to send) looks like this:
syscon@0 { compatible = "syscon", "simple-mfd"; reg = <0x0 0x2000>; clock { compatible = "toshiba,tc9564-clock"; #clock-cells = <1>; }; };A reset node will also go inside the syscon, so there is another function for that MFD.
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The regmap belongs to the parent, and is looked up this way:
regmap = syscon_node_to_regmap(dev_of_node(dev->parent));That's driver code, so irrelevant. So how does this solve my comment from v1?
I'm trying Krzysztof.
The clock controller uses two registers,
0x1004and0x100c, to manage whether a set of clock signals are enabled or not. (The reset controller uses two adjacent registers,0x1008and0x1010, to manage whether a set of reset signals are asserted or not.)You said "no resources except a small address space" and I guess it's not clear to me what size is "big enough" to warrant representing something as a separate device.
*One* of the managed clocks is a 25 MHz clock, exposed through a pin on the SoC. That one clock signal is therefore usable by the platform (although on the RB3gen2 it's not used).
Rather than expose the register addresses in the clock node, a syscon is defined, covering 8 KB, and the actual offsets used are just defined in the clock and reset driver source code.
If that's not the right thing to do, please say that.
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What's more, I still do not see any usage of these clocks outside. And I still did not receive actual answers (or I missed them) how these clocks are routed OUTSIDE of the connector. You said for example:
"Ultimately the TC9564 SoC has a single 25 MHz input clock,". . .
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The single exposed clock *might* justify presenting the clock controller device in devicetree. There are also resets exposed externally via GPIOs, and these control external entities (PHYs).
I cannot find any of these exposed. Please point me to DTS code showing this.
It is not used by this platform, but is available for other platforms to use. Its name is "REFCLKO" and is exposed on ball C17 of the SoC, if a platform designer decided to use it.
I only mention its existence as a reason to justify defining the clock as a separate device, but I realize you are arguing that I should do it somehow differently.
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-Alex
While on the topic of description, I'm little bit concerned that this controller does not any input ? Does it have an on-board oscillator somehow ?
No, it has an external fixed 25 MHz input, and this is a good point, that should be represented.
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None of the clocks described in your driver take a parent from what I can see. It is as if the clocks of this device are generated out of thin air. Is it really how this works ?
No, you're right to point this out. Thank you.
-Alex
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Best regards,
Krzysztof
Re: [PATCH v2 1/3] dt-bindings: clock: introduce toshiba,tc9564-clock.yaml
In reply to Alex ElderQuoted 50 lines · Alex Elder
Quoted 9 lines · Krzysztof Kozlowski
Quoted 8 lines · Alex Elder
Quoted 7 lines · Krzysztof Kozlowski
Quoted 6 lines · Alex Elder
Define the binding for the clock controller functionality present in the Toshiba TC9564 SoC.
Co-developed-by Daniel Thompson <[email protected]>Signed-off-by Daniel Thompson <[email protected]>Signed-off-by Alex Elder <[email protected]>. . .
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Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml line 34
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Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml new file +8
-0+properties: + compatible: + const: toshiba,tc9564-clock + + toshiba,config-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle for the configuration space system controller.I do not see my previous comment addressed - you have no resources here, so this belongs to the parent. You responded something about pci-ep, but the parent is not pci-ep. Open your code:
https://lore.kernel.org/lkml/[email protected]/Quoted 7 lines
I clearly see code like:
syscon { clock@ { }; };so I do not understand what pci-ep has anything to do here.
What I have now (about to send) looks like this:
syscon@0 { compatible = "syscon", "simple-mfd"; reg = <0x0 0x2000>; clock { compatible = "toshiba,tc9564-clock"; #clock-cells = <1>; }; };A reset node will also go inside the syscon, so there is another function for that MFD.
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The regmap belongs to the parent, and is looked up this way:
regmap = syscon_node_to_regmap(dev_of_node(dev->parent));That's driver code, so irrelevant. So how does this solve my comment from v1?
I'm trying Krzysztof.
In v1 I asked to fold the node into the parent. v2 did not have it. v3, which you are preparing, still has no node folded, because they are separate.
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The clock controller uses two registers,
0x1004and0x100c, to manage whether a set of clock signals are enabled or not. (The reset controller uses two adjacent registers,0x1008and0x1010, to manage whether a set of reset signals are asserted or not.)You said "no resources except a small address space" and I guess it's not clear to me what size is "big enough" to warrant representing something as a separate device.
*One* of the managed clocks is a 25 MHz clock, exposed through a pin on the SoC. That one clock signal is therefore usable by the platform (although on the RB3gen2 it's not used).
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Rather than expose the register addresses in the clock node, a syscon is defined, covering 8 KB, and the actual offsets used are just defined in the clock and reset driver source code.
If that's not the right thing to do, please say that.
Nodes should be squashed.
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What's more, I still do not see any usage of these clocks outside. And I still did not receive actual answers (or I missed them) how these clocks are routed OUTSIDE of the connector. You said for example:
"Ultimately the TC9564 SoC has a single 25 MHz input clock,". . .
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The single exposed clock *might* justify presenting the clock controller device in devicetree. There are also resets exposed externally via GPIOs, and these control external entities (PHYs).
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I cannot find any of these exposed. Please point me to DTS code showing this.
It is not used by this platform, but is available for other platforms to use. Its name is "REFCLKO" and is exposed on ball C17 of the SoC, if a platform designer decided to use it.
Yeah, but you do not describe the SoC but PCI EP device, thus my claim is that clocks cannot be used by the host. The SoC itself for different hardware uses would have different binding, so that's not an argument to have anything here, unless these different uses are also documented here.
Best regards,
Krzysztof
Re: [PATCH v2 1/3] dt-bindings: clock: introduce toshiba,tc9564-clock.yaml
Quoted 55 lines · Krzysztof Kozlowski
Quoted 54 lines · Alex Elder
Quoted 9 lines · Krzysztof Kozlowski
Quoted 8 lines · Alex Elder
Quoted 7 lines · Krzysztof Kozlowski
Quoted 6 lines · Alex Elder
Define the binding for the clock controller functionality present in the Toshiba TC9564 SoC.
Co-developed-by Daniel Thompson <[email protected]>Signed-off-by Daniel Thompson <[email protected]>Signed-off-by Alex Elder <[email protected]>. . .
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Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml line 34
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Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml new file +8
-0+properties: + compatible: + const: toshiba,tc9564-clock + + toshiba,config-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle for the configuration space system controller.I do not see my previous comment addressed - you have no resources here, so this belongs to the parent. You responded something about pci-ep, but the parent is not pci-ep. Open your code:
https://lore.kernel.org/lkml/[email protected]/Quoted 7 lines
I clearly see code like:
syscon { clock@ { }; };so I do not understand what pci-ep has anything to do here.
What I have now (about to send) looks like this:
syscon@0 { compatible = "syscon", "simple-mfd"; reg = <0x0 0x2000>; clock { compatible = "toshiba,tc9564-clock"; #clock-cells = <1>; }; };A reset node will also go inside the syscon, so there is another function for that MFD.
The regmap belongs to the parent, and is looked up this way:
regmap = syscon_node_to_regmap(dev_of_node(dev->parent));
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That's driver code, so irrelevant. So how does this solve my comment from v1?
I'm trying Krzysztof.
In v1 I asked to fold the node into the parent. v2 did not have it. v3, which you are preparing, still has no node folded, because they are separate.
Are you saying to fold it into the PCI function?
If so, could the PCI function be a clock provider and define #clock-cells (and #reset-cells)?
Because as things stand now, clock and reset are used by the two DWMAC Ethernet interfaces as well as a separate interrupt controller (one for each PCI function).
It sounds a little like you might prefer everything being wrapped up in the DWMAC driver, as we originally did six months ago.
-Alex
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The clock controller uses two registers,
0x1004and0x100c, to manage whether a set of clock signals are enabled or not. (The reset controller uses two adjacent registers,0x1008and0x1010, to manage whether a set of reset signals are asserted or not.)You said "no resources except a small address space" and I guess it's not clear to me what size is "big enough" to warrant representing something as a separate device.
*One* of the managed clocks is a 25 MHz clock, exposed through a pin on the SoC. That one clock signal is therefore usable by the platform (although on the RB3gen2 it's not used).
Quoted 6 lines
Rather than expose the register addresses in the clock node, a syscon is defined, covering 8 KB, and the actual offsets used are just defined in the clock and reset driver source code.
If that's not the right thing to do, please say that.
Nodes should be squashed.
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What's more, I still do not see any usage of these clocks outside. And I still did not receive actual answers (or I missed them) how these clocks are routed OUTSIDE of the connector. You said for example:
"Ultimately the TC9564 SoC has a single 25 MHz input clock,". . .
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The single exposed clock *might* justify presenting the clock controller device in devicetree. There are also resets exposed externally via GPIOs, and these control external entities (PHYs).
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I cannot find any of these exposed. Please point me to DTS code showing this.
It is not used by this platform, but is available for other platforms to use. Its name is "REFCLKO" and is exposed on ball C17 of the SoC, if a platform designer decided to use it.
Yeah, but you do not describe the SoC but PCI EP device, thus my claim is that clocks cannot be used by the host. The SoC itself for different hardware uses would have different binding, so that's not an argument to have anything here, unless these different uses are also documented here.
Best regards,
Krzysztof
Re: [PATCH v2 1/3] dt-bindings: clock: introduce toshiba,tc9564-clock.yaml
Quoted 59 lines · Alex Elder
Quoted 58 lines · Krzysztof Kozlowski
Quoted 57 lines · Alex Elder
Quoted 9 lines · Krzysztof Kozlowski
Quoted 8 lines · Alex Elder
Quoted 7 lines · Krzysztof Kozlowski
Quoted 6 lines · Alex Elder
Define the binding for the clock controller functionality present in the Toshiba TC9564 SoC.
Co-developed-by Daniel Thompson <[email protected]>Signed-off-by Daniel Thompson <[email protected]>Signed-off-by Alex Elder <[email protected]>. . .
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Review
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(quoted diff) +8
-0+properties: + compatible: + const: toshiba,tc9564-clock + + toshiba,config-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle for the configuration space system controller.I do not see my previous comment addressed - you have no resources here, so this belongs to the parent. You responded something about pci-ep, but the parent is not pci-ep. Open your code:
https://lore.kernel.org/lkml/[email protected]/Quoted 7 lines
I clearly see code like:
syscon { clock@ { }; };so I do not understand what pci-ep has anything to do here.
What I have now (about to send) looks like this:
syscon@0 { compatible = "syscon", "simple-mfd"; reg = <0x0 0x2000>; clock { compatible = "toshiba,tc9564-clock"; #clock-cells = <1>; }; };Quoted 6 lines
A reset node will also go inside the syscon, so there is another function for that MFD.
The regmap belongs to the parent, and is looked up this way:
regmap = syscon_node_to_regmap(dev_of_node(dev->parent));That's driver code, so irrelevant. So how does this solve my comment from v1?
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I'm trying Krzysztof.
In v1 I asked to fold the node into the parent. v2 did not have it. v3, which you are preparing, still has no node folded, because they are separate.
Are you saying to fold it into the PCI function?
I do not see in the example the parent being PCI function, so I do not understand that. What is this node? What is its parent?
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If so, could the PCI function be a clock provider and define #clock-cells (and #reset-cells)?
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Because as things stand now, clock and reset are used by the two DWMAC Ethernet interfaces as well as a separate interrupt controller (one for each PCI function).
It sounds a little like you might prefer everything being wrapped up in the DWMAC driver, as we originally did six months ago.
Not sure which patchset you refer to - v1 was in September.
Best regards,
Krzysztof
PATCH v2 2/3 clk: toshiba: introduce a TC9564 SoC clock driver
In reply to Alex ElderDefine a new platform driver that manages clocks implemented by the Toshiba TC9564 SoC. There are 21 clocks that can be enabled and disabled. Two of these are reserved, so only 19 can be managed.
Two registers manage the state of the clocks. The registers are accessed via a regmap supplied by a system controller, because the region of memory accessed is shared with other drivers.
Access to the memory region is provided via a BAR on a PCIe endpoint function embedded in the TC9564 SoC. For that reason the PCIe clock cannot be manipulated by this driver (it is assumed to be enabled). Similarly, control is not available for the I2C clock, because the PCIe subsystem on the TC9564 relies on I2C.
---
v2: - Only implement clock functionality, not reset functionality
- Get the definition of of_device_id from <linux/device_id/of.h>
- Dropped a comma that followed a ternminating empty array entry
- Config option COMMON_CLK_TC9564 now selects MFD_SYSCON
- Clarified in config help text that the reset and stmmac drivers also use the config syscon
MAINTAINERS | 1 + drivers/clk/Kconfig | 12 ++ drivers/clk/Makefile | 1 + drivers/clk/clk-tc9564.c | 262 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 276 insertions(+) create mode 100644 drivers/clk/clk-tc9564.c
MAINTAINERS +1 -0
@@ -28133,6 +28133,7 @@ M: Alex Elder <[email protected]> M: Daniel Thompson <[email protected]> S: Maintained F: Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml +F: drivers/clk/clk-tc9564.c F: include/dt-bindings/clock/toshiba,tc9564.h TOSHIBA TC9564 PCI DRIVER
drivers/clk/Kconfig +12 -0
@@ -293,6 +293,18 @@ config COMMON_CLK_S2MPS11 clock. These multi-function devices have two (S2MPS14) or three (S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each. +config COMMON_CLK_TC9564 + tristate "Toshiba TC9564 clock support" + depends on TC9564_PCI + select MFD_SYSCON + default TC9564_PCI + help + This enables support for the clock controller embedded in the + Toshiba TC9564 SoC. The state of each clock is controlled via + MMIO to a region managed by a system controller; this ensures + access to the region is coordinated between this and the reset + and XGMAC (stmmac) drivers. + config CLK_TWL tristate "Clock driver for the TWL PMIC family" depends on TWL4030_CORE
drivers/clk/Makefile +1 -0
@@ -111,6 +111,7 @@ obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o obj-$(CONFIG_COMMON_CLK_SP7021) += clk-sp7021.o obj-$(CONFIG_COMMON_CLK_STM32F) += clk-stm32f4.o obj-$(CONFIG_COMMON_CLK_STM32H7) += clk-stm32h7.o +obj-$(CONFIG_COMMON_CLK_TC9564) += clk-tc9564.o obj-$(CONFIG_COMMON_CLK_TPS68470) += clk-tps68470.o obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o obj-$(CONFIG_CLK_TWL) += clk-twl.o
drivers/clk/clk-tc9564.c new file +262 -0
262 lines not on this page · raw message
Signature · 1 line
2.53.0
Re: [PATCH v2 2/3] clk: toshiba: introduce a TC9564 SoC clock driver
Quoted 14 lines · Alex Elder
Define a new platform driver that manages clocks implemented by the Toshiba TC9564 SoC. There are 21 clocks that can be enabled and disabled. Two of these are reserved, so only 19 can be managed.
Two registers manage the state of the clocks. The registers are accessed via a regmap supplied by a system controller, because the region of memory accessed is shared with other drivers.
Access to the memory region is provided via a BAR on a PCIe endpoint function embedded in the TC9564 SoC. For that reason the PCIe clock cannot be manipulated by this driver (it is assumed to be enabled). Similarly, control is not available for the I2C clock, because the PCIe subsystem on the TC9564 relies on I2C.
Quoted 3 lines
Co-developed-by Daniel Thompson <[email protected]>Signed-off-by Daniel Thompson <[email protected]>Signed-off-by Alex Elder <[email protected]>
PATCH v2 3/3 arm64: dts: qcom: qcs6490-rb3gen2: add the clock controller
In reply to Alex ElderThe clock controller within the TC9564 SoC is accessed via a PCI endpoint bus through BAR 4 of the first embedded PCIe function. A syscon node is created to provide access to a range of memory that is used by the clock controller and shared with other devices.
---
v2: - Moved the clock devicetree node to be a peer (rather than a child) of
the syscon node
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-)
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +15 -1
@@ -9,6 +9,7 @@ #define PM7250B_SID 8 #define PM7250B_SID1 9 +#include <dt-bindings/clock/toshiba,tc9564.h> #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h> #include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h> #include <dt-bindings/leds/common.h>
@@ -961,7 +962,7 @@ dev@0,0 { #size-cells = <2>; ranges; /* This will be updated dynamically */ - pci-ep-bus@4 { + pcie_s1b5d0f0_bar4_bus: pci-ep-bus@4 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>;
@@ -989,6 +990,19 @@ pci-ep-bus@4 { }; }; +&pcie_s1b5d0f0_bar4_bus { + tc9564_config_syscon0: syscon@0 { + compatible = "syscon"; + reg = <0x0 0x2000>; + }; + + tc9564_clock0: clock { + compatible = "toshiba,tc9564-clock"; + toshiba,config-syscon = <&tc9564_config_syscon0>; + #clock-cells = <1>; + }; +}; + &pm7325_gpios { kypd_vol_up_n: kypd-vol-up-n-state { pins = "gpio6";
Signature · 1 line
2.53.0
Re: [PATCH v2 3/3] arm64: dts: qcom: qcs6490-rb3gen2: add the clock controller
Quoted 11 lines · Alex Elder
The clock controller within the TC9564 SoC is accessed via a PCI endpoint bus through BAR 4 of the first embedded PCIe function. A syscon node is created to provide access to a range of memory that is used by the clock controller and shared with other devices.
Co-developed-by Daniel Thompson <[email protected]>Signed-off-by Daniel Thompson <[email protected]>Signed-off-by Alex Elder <[email protected]>---
v2: - Moved the clock devicetree node to be a peer (rather than a child) of
the syscon node
Whoops. I dropped the "reg" property, and that means the change mentioned above leads to a warning.
Either make them peers, but keep the clock node "reg" property, or drop "reg" and make the clock node subordinate to the syscon.
I will address this in version 3 of this series, but (unless someone suggests otherwise) I'll wait to get feedback on the rest of the series before I send that.
-Alex
Quoted 45 lines
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-)arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +15
-1@@ -9,6 +9,7 @@ #define PM7250B_SID 8 #define PM7250B_SID1 9 +#include <dt-bindings/clock/toshiba,tc9564.h> #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h> #include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h> #include <dt-bindings/leds/common.h>@@ -961,7 +962,7 @@ dev@0,0 { #size-cells = <2>; ranges; /* This will be updated dynamically */ - pci-ep-bus@4 { + pcie_s1b5d0f0_bar4_bus: pci-ep-bus@4 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>;@@ -989,6 +990,19 @@ pci-ep-bus@4 { }; }; +&pcie_s1b5d0f0_bar4_bus { + tc9564_config_syscon0: syscon@0 { + compatible = "syscon"; + reg = <0x0 0x2000>; + }; + + tc9564_clock0: clock { + compatible = "toshiba,tc9564-clock"; + toshiba,config-syscon = <&tc9564_config_syscon0>; + #clock-cells = <1>; + }; +}; + &pm7325_gpios { kypd_vol_up_n: kypd-vol-up-n-state { pins = "gpio6";