What is the truth about Linux 2.4's RAM limitations?
Quoted 10 lines · Brian Gerst
Jesse Pollard wrote:
> If the entire page table were given to a user, then a full cache > flush would have to be done on every context switch and system > call. That would be very slow, but would allow a full 4G address > for the user.
Quoted 5 lines
A full cache flush would be needed at every entry into the kernel, including hardware interrupts. Very poor for performance.
Why would a cache flush be necessary at all? I assume ia32 caches where physically not virtually mapped?
Because the entire virtual mapping is replaced by that of the kernel. This would invalidate the entire cache table. It was also pointed out that this would have to be done for every interrupt too.
-------------------------------------------------------------------------
Jesse I Pollard, II
Email: [email protected]
Any opinions expressed are solely my own.
Quoted 9 lines · Jesse Pollard
Quoted 5 lines
A full cache flush would be needed at every entry into the kernel,
including hardware interrupts. Very poor for performance.Why would a cache flush be necessary at all? I assume ia32 caches where physically not virtually mapped?
Because the entire virtual mapping is replaced by that of the kernel. This would invalidate the entire cache table. It was also pointed out that this would have to be done for every interrupt too.
If the cache were physically indexed and tagged, this would not be the case; changes in mapping would be irrelevant. If someone has a reference that describes IA-32 cache tags in detail, I'd like to know about it.
TLBs are another story, though on some other architectures they're not a problem either. UltraSPARC, for example, maps the entire kernel with a couple or three reserved TLB entries (at least Solaris does). Of course, SPARC has hardware contexts, which are helpful in this regard.
Signature · 1 line
/Jonathan Lundell.