big resync x86 setup code for 2.2.20
PATCH 1/1 big resync x86 setup code for 2.2.20
I just backported a lot of stuff from 2.4's setup.c and friends.
Some of this stuff hasn't been updated since ~2.3.99 or so, which was just before hpa's big cleanup in that area.
Summary of changes:
- updated bluesmoke.c
- MSR number typo bugfix
- extra non-Intel architecture support.
- setup.c
- P4 right justified name string fixup
- Fix up c->x86_cache_size on machines with 0K L2 cache
- Fix up cache size on Cyrix MediaGx
- Enable MMX extensions on MII (Alan)
- Fix up misplaced brace in Cyrix setup path.
- Add recognition of RiSE CPUs.
- Update cpuid_level when disabling serial number (Hugh Dickins)
- Initialise Centaur CPUs from the same codepath as the other vendors instead of in print_cpu_info()
- Recognise all types of Celerons/Mobile PII's
- boottime 'serialnumber' option to leave serial # enabled.
- Improved Centaur Winchip handling.
- Recognise 386/486 in c->x86_model_id (Cesar Barros)
- Several bug workarounds moved from bugs.h to setup.c
- Other small cleanups.
- Overall source cleaning to bring in line with 2.4
The 2.4 stuff is still cleaner than 2.2's, but this at least gets things a lot closer to each other making any future resyncs easier. There's still some outstanding bits, such as PIII Tualatin fixups, but I'll wait until they're in 2.4 for a while before merging.
Due to the huge size of this diff, there may be some breakage, so I'd like to get some testing before sending this to Alan for 2.2.21pre inclusion. Let me know of any no-boot/strange output/cpuinfo cases, and I'll see what goes.
Patch is against 2.2.20
arch/i386/kernel/bluesmoke.c +149 -19
@@ -1,17 +1,18 @@ -/* -* Machine Check Handler For PII/PIII -*/ -#include <linux/config.h> +#include <linux/init.h> #include <linux/types.h> #include <linux/kernel.h> #include <linux/sched.h> #include <asm/processor.h> #include <asm/msr.h> -static int banks =0 ; +/* +* Machine Check Handler For PII/PIII +*/ + +static int banks; -void mcheck_fault (void ) +static void intel_machine_check (struct pt_regs * regs,long error_code) {int recover=1 ;u32 alow, ahigh, high, low;
@@ -37,7 +38,7 @@ high&=~(1 <<31 );if (high&(1 <<27 )) { -rdmsr (0x403 +i*4 , alow, ahigh); +rdmsr (0x402 +i*4 , alow, ahigh);printk ("[%08x%08x]" , alow, ahigh); }if (high&(1 <<26 ))
@@ -50,7 +51,7 @@/* Clear it */ wrmsr (0x401 +i*4 ,0UL ,0UL );/* Serialize */ -mb (); +wmb (); } }
@@ -63,31 +64,101 @@wrmsr (0x17a ,mcgstl, mcgsth); } +/* +* Machine check handler for Pentium class Intel +*/ + +static void pentium_machine_check (struct pt_regs * regs,long error_code) +{ +u32 loaddr, hi, lotype; +rdmsr (0x0 , loaddr, hi); +rdmsr (0x1 , lotype, hi); +printk (KERN_EMERG "CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n" ,smp_processor_id (), loaddr, lotype); +if (lotype&(1 <<5 )) +printk (KERN_EMERG "CPU#%d: Possible thermal failure (CPU on fire ?).\n" ,smp_processor_id ()); +}/* -* This has to be run for each processor +* Machine check handler for WinChip C6 */ -void mcheck_init (void ) +static void winchip_machine_check (struct pt_regs * regs,long error_code) +{ +printk (KERN_EMERG "CPU#%d: Machine Check Exception.\n" ,smp_processor_id ()); +} + +/* +* Handle unconfigured int18 (should never happen) +*/ + +static void unexpected_machine_check (struct pt_regs * regs,long error_code) +{ +printk (KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n" ,smp_processor_id ()); +} + +/* +* Call the installed machine check handler for this CPU setup. +*/ + +static void (*machine_check_vector)(struct pt_regs *,long error_code) = unexpected_machine_check; + +void do_machine_check (struct pt_regs * regs,long error_code) +{ +machine_check_vector (regs, error_code); +} + +/* +* Set up machine check reporting for Intel processors +*/ + +void __init intel_mcheck_init (struct cpuinfo_x86 *c) {u32 l, h;int i; -struct cpuinfo_x86 *c; -static int done=0 ; +static int done; + +/* +* Check for MCE support +*/ - c=cpu_data+smp_processor_id (); +if (!(c->x86_capability&X86_FEATURE_MCE )) +return ; -if (c->x86_vendor!=X86_VENDOR_INTEL ) -return ; +/* +* Pentium machine check +*/ -if (!(c->x86_capability&X86_FEATURE_MCE )) +if (c->x86 ==5 ) + { + machine_check_vector = pentium_machine_check; +wmb (); +/* Read registers before enabling */ +rdmsr (0x0 , l, h); +rdmsr (0x1 , l, h); +if (done==0 ) +printk (KERN_INFO "Intel old style machine check architecture supported.\n" ); +/* Enable MCE */ + __asm__ __volatile__ ( +"movl %%cr4, %%eax\n\t" +"orl $0x40, %%eax\n\t" +"movl %%eax, %%cr4\n\t" : : :"eax" ); +printk (KERN_INFO "Intel old style machine check reporting enabled on CPU#%d.\n" ,smp_processor_id ());return ; - + } + + +/* +* Check for PPro style MCA +*/ +if (!(c->x86_capability&X86_FEATURE_MCA ))return ;/* Ok machine check is available */ + machine_check_vector = intel_machine_check; +wmb (); +if (done==0 )printk (KERN_INFO "Intel machine check architecture supported.\n" );rdmsr (0x179 , l, h);
@@ -102,10 +173,69 @@ {wrmsr (0x401 +4 *i,0x0 ,0x0 ); } +set_in_cr4 (X86_CR4_MCE ); +printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n" ,smp_processor_id ()); + done=1 ; +} + +/* +* Set up machine check reporting on the Winchip C6 series +*/ + +static void __init winchip_mcheck_init (struct cpuinfo_x86 *c) +{ +u32 lo, hi; +/* Not supported on C3 */ +if (c->x86 !=5 ) +return ; +/* Winchip C6 */ + machine_check_vector = winchip_machine_check; +wmb (); +rdmsr (0x107 , lo, hi); + lo|= (1 <<2 );/* Enable EIERRINT (int 18 MCE) */ + lo&= ~(1 <<4 );/* Enable MCE */ +wrmsr (0x107 , lo, hi); __asm__ __volatile__ ("movl %%cr4, %%eax\n\t" "orl $0x40, %%eax\n\t" "movl %%eax, %%cr4\n\t" : : :"eax" ); -printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n" ,smp_processor_id ()); - done=1 ; +printk (KERN_INFO "Winchip machine check reporting enabled on CPU#%d.\n" ,smp_processor_id ()); +} + + +/* +* This has to be run for each processor +*/ + + +static int mce_disabled =0 ; + +void __init mcheck_init (struct cpuinfo_x86 *c) +{ +if (mce_disabled) +return ; + +switch (c->x86_vendor) + { +case X86_VENDOR_AMD : +/* +* AMD K7 machine check is Intel like +*/ +if (c->x86 ==6 ) +intel_mcheck_init (c); +break ; +case X86_VENDOR_INTEL : +intel_mcheck_init (c); +break ; +case X86_VENDOR_CENTAUR : +winchip_mcheck_init (c); +break ; + } +} + +static int __init mcheck_disable (char *str,int *unused) +{ + mce_disabled =1 ; +return 0 ; } +__setup ("nomce" , mcheck_disable);
arch/i386/kernel/entry.S +1 -1
@@ -366,7 +366,7 @@ ENTRY(machine_check) pushl $0 - pushl $ SYMBOL_NAME(mcheck_fault) + pushl $ SYMBOL_NAME(do_machine_check) jmp error_code ENTRY(spurious_interrupt_bug)
arch/i386/kernel/setup.c +304 -215
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arch/i386/mm/init.c +0 -25
@@ -185,33 +185,8 @@extern char _text, _etext, _edata, __bss_start, _end;extern char __init_begin, __init_end; -#define X86_CR4_VME 0x0001/* enable vm86 extensions */ -#define X86_CR4_PVI 0x0002/* virtual interrupts flag enable */ -#define X86_CR4_TSD 0x0004/* disable time stamp at ipl 3 */ -#define X86_CR4_DE 0x0008/* enable debugging extensions */ -#define X86_CR4_PSE 0x0010/* enable page size extensions */ -#define X86_CR4_PAE 0x0020/* enable physical address extensions */ -#define X86_CR4_MCE 0x0040/* Machine check enable */ -#define X86_CR4_PGE 0x0080/* enable global pages */ -#define X86_CR4_PCE 0x0100/* enable performance counters at ipl 3 */ - -/* -* Save the cr4 feature set we're using (ie -* Pentium 4MB enable and PPro Global page -* enable), so that any CPU's that boot up -* after us can get the correct flags. -*/ unsigned long mmu_cr4_features__initdata =0 ; -static inline void set_in_cr4 (unsigned long mask) -{ - mmu_cr4_features |= mask; - __asm__("movl %%cr4,%%eax\n\t" -"orl %0,%%eax\n\t" -"movl %%eax,%%cr4\n" - : :"irg" (mask) - :"ax" ); -}/* * allocate page table(s) for compile-time fixed mappings
include/asm-i386/processor.h +97 -1
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Signature · 2 lines
| Dave Jones. http://www.codemonkey.org.uk | SuSE Labs .