to swap or not to swap

Can someone please explain this to me?

It looks like some BE architectures define {read,write}[wl] to do LE swapping (sparc, mipsel, ppc, etc) but others don't (s390, parisc). What is the "correct" behavior?

The inX/outX interfaces are all internal-swapped to LE.

randolph

   @..@                                         http://www.TauSq.org/
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depends on the PCI bridge and MMU whether you need to do bytesexswapping in software or not. see section 9 in the Dino ERS, page 61 for how PA does this.

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Empirically I've found this not to be the case. For example, if i need to write 0x01 to byte 0 of a 16-bit PCI register, I've found I need to do:

writew(0x0100, addr) on parisc
vs
writew(0x0001, addr) on x86

Grant also seems to be of the opinion that cpu data needs to be swapped before written to PCI devices... so does that mean that if i wrote something like:

writew(cpu_to_le16(foo), addr)

then on things like parisc it gets swapped once, and on things like sparc it gets swapped twice?

randolph

   @..@                                         http://www.TauSq.org/
  (----)
 ( >__< )
 ^^ ~~ ^^

maybe that's a bug in how sparc code works?

For parisc, the above is correct for (nearly) all PCI devices. (I hedge since odd PCI devices might want cpu_to_be16() instead).

And don't forget that control data read by the PCI device via DMA has to be "endian corrected" too.

PA HW implements what I've heard called "address invariance". IIRC, m700-10 (r4000 mips, Olivetti) does the same thing. I think Dino Documentation calls this "byte is byte". Ie byte stream offsets are the same regardless of how they are address by either DMA or PIO from either CPU or PCI device.

The result is multi-byte data (ie short/int) has to be swapped when read/written by the PArisc CPU and the addresses don't change.

HTH,
grant

Constant swaps get optimised out by the compiler in theory though.