PCI updates - 32-bit IO support
PATCH 1/1 PCI updates - 32-bit IO support
I have here a system which requires 32-bit IO addressing on its PCI busses. Currently, Linux zeros the upper IO base/limit registers on all PCI bridges, which prevents addresses being forwarded on this system.
The following patch the upper IO base/limit registers to be set appropriately by the PCI layer.
This patch is being sent for review, and is targetted solely at 2.5.
drivers/pci/setup-bus.c +4 -1
@@ -148,7 +181,10 @@pci_write_config_dword (bridge,PCI_IO_BASE , l);/* Clear upper 16 bits of I/O base/limit. */ -pci_write_config_dword (bridge,PCI_IO_BASE_UPPER16 ,0 ); +pci_write_config_word (bridge,PCI_IO_BASE_UPPER16 , + ranges.io_start >>16 ); +pci_write_config_word (bridge,PCI_IO_LIMIT_UPPER16 , + ranges.io_end >>16 );/* Clear out the upper 32 bits of PREF base/limit. */ pci_write_config_dword (bridge,PCI_PREF_BASE_UPPER32 ,0 );
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Russell King ([email protected]) The developer of ARM Linux
http://www.arm.linux.org.uk/personal/aboutme.html
Followup to: <[email protected]> By author: Russell King <[email protected]> In newsgroup: linux.dev.kernel
Quoted 15 lines
I have here a system which requires 32-bit IO addressing on its PCI busses. Currently, Linux zeros the upper IO base/limit registers on all PCI bridges, which prevents addresses being forwarded on this system.
The following patch the upper IO base/limit registers to be set appropriately by the PCI layer.
This patch is being sent for review, and is targetted solely at 2.5.
diff -ur
orig/drivers/pci/setup-bus.clinux/drivers/pci/setup-bus.c
drivers/pci/setup-bus.c line 188
Quoted 9 lines
drivers/pci/setup-bus.c +4
-1@@ -148,7 +181,10 @@pci_write_config_dword (bridge,PCI_IO_BASE , l);/* Clear upper 16 bits of I/O base/limit. */ -pci_write_config_dword (bridge,PCI_IO_BASE_UPPER16 ,0 ); +pci_write_config_word (bridge,PCI_IO_BASE_UPPER16 , + ranges.io_start >>16 ); +pci_write_config_word (bridge,PCI_IO_LIMIT_UPPER16 , + ranges.io_end >>16 );
You probably need to verify that 32-bit support is available (both on the bridge and the peripherals), but if they are, there's no reason not to use it on non-x86 architectures...
-hpa
Signature · 3 lines
<[email protected]> at work, <[email protected]> in private! "Unix gives you enough rope to shoot yourself in the foot." http://www.zytor.com/~hpa/puzzle.txt <[email protected]>
From: "H. Peter Anvin" <[email protected]>
Date: 19 Dec 2001 19:37:46 -0800
You probably need to verify that 32-bit support is available (both on the bridge and the peripherals), but if they are, there's no reason not to use it on non-x86 architectures...
Don't the PCI specs actually talk about 24-bits in fact?
Russell does you box really have the full 32-bits or is it really just 24-bits?
Quoted 9 lines · David S. Miller
From: "H. Peter Anvin" <[email protected]>
Date: 19 Dec 2001 19:37:46 -0800You probably need to verify that 32-bit support is available (both on the bridge and the peripherals), but if they are, there's no reason not to use it on non-x86 architectures...
Don't the PCI specs actually talk about 24-bits in fact?
No. IOIO is 32 bits on PCI; however, it is legal to hardwire the top 16 bits to zero. It's something like 26 bits on HyperTransport.
-hpa
Quoted 4 lines · David S. Miller
Don't the PCI specs actually talk about 24-bits in fact?
Russell does you box really have the full 32-bits or is it really just 24-bits?
Shrug - the chip documentation isn't good enough to indicate either.
What I do know is:
- setting the bridge and eepro100 up with 16-bit IO addresses causes PCI master aborts.
- setting the bridge and eepro100 up with 32-bit IO addresses which correspond to the host MMIO region, it works perfectly.
It appears that the first bridge converts the mmio access into a PCI IO read/write cycle without any address translation. So, when I access mmio 0x90011000, it would appear to cause a PCI IO cycle at the same address.
The MMIO region for this bus is 0x90010000 - 0x9001ffff, so its impossible to test the effect of different upper 16-bits.
I suppose I could waste some time by getting Linux to generate lots of IO cycles and scoping the PCI bus lines to find the PCI address, but I think its rather academic in light of the above.
--
Russell King ([email protected]) The developer of ARM Linux
http://www.arm.linux.org.uk/personal/aboutme.html
Quoted 2 lines · Russell King
- setting the bridge and eepro100 up with 32-bit IO addresses which correspond to the host MMIO region, it works perfectly.
Note that this wouldn't work with DEC 2105x PCI-PCI bridges, which support only 16 bit I/O forwarding.
However, the patch is totally harmless for architectures limiting I/O to 64K.
Ivan.