strange dmesg output on athlon notebook

Hi!

I see this in syslog:

CPU: Before vendor init, caps: 0183fbff c1c7fbff 00000000, vendor = 2 Enabling disabled K7/SSE Support.
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 256K (64 bytes/line)
CPU: After vendor init, caps: 0383fbff c1c7fbff 00000000 00000000 Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#0.

CPU:     After generic, caps: 0383fbff c1c7fbff 00000000 00000000
CPU:             Common caps: 0383fbff c1c7fbff 00000000 00000000

Enabling fast FPU save and restore... done.
Enabling unmasked SIMD FPU exception support... done. Checking 'hlt' instruction... OK.
POSIX conformance testing by UNIFIX
CPU: Before vendor init, caps: 0383fbff c1c7fbff 00000000, vendor = 2
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 256K (64 bytes/line)
CPU: After vendor init, caps: 0383fbff c1c7fbff 00000000 00000000 Intel machine check reporting enabled on CPU#0.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

CPU:     After generic, caps: 0383fbff c1c7fbff 00000000 00000000
CPU:             Common caps: 0383fbff c1c7fbff 00000000 00000000

Why _Intel_ machine check? And why it says CPU: After vendor init twice? [This is 2.5.6-acpi...]
Pavel

(about SSSCA) "I don't say this lightly.  However, I really think that the U.S.
no longer is classifiable as a democracy, but rather as a plutocracy." --hpa

AMD supports the intel machine check on Athlon

Hi!

Unless I made mistake, it was UP kernel.
Pavel

Casualities in World Trade Center: ~3k dead inside the building,
cryptography in U.S.A. and free speech in Czech Republic.

Same reason the Athlon has Intel style MTRRs.
Though digging through the docs the last day or so, the MCE isn't 100% compatable. I'll work on this sometime soon.

SMP kernel ?
We init the boot CPU twice on SMP iirc.

| Dave Jones.        http://www.codemonkey.org.uk
| SuSE Labs