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WARNING: unexpected IO-APIC

DISCUSSION Michael Arndt 1 participant 1 message Jul 8, 2002

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Hello

a Dual CPU Board gets the following error messages with respect to MTR / APIC (below in detail)

IO APIC #2......
.... register #00: 02000000
....... : physical APIC id: 02
.... register #01: 00178020
....... : max redirection entries: 0017
....... : IO APIC version: 0020
WARNING: unexpected IO-APIC, please mail
to [email protected]
mtrr: your CPUs had inconsistent fixed MTRR settings
mtrr: probably your BIOS does not setup all CPUs

      CPU: 2 x Intel XEON 2.2 GHZ
   Kernel: 2.4.9-21smp #1 SMP Thu Jan 17 14:01:48 EST 2002 i686 unknown

If there is any Feedback, please pm, i am not on the list.

Complete Output:

Intel MultiProcessor Specification v1.4
Virtual Wire compatibility mode.
OEM ID: OEM00000 Product ID: PROD00000000 APIC at: 0xFEE00000 Processor #0 Unknown CPU [15:2] APIC version 17 Processor #1 Unknown CPU [15:2] APIC version 17
I/O APIC #2 Version 17 at 0xFEC00000.
Processors: 2

CPU: Physical Processor ID: 3
Intel machine check reporting enabled on CPU#1.

CPU: After vendor init, caps: 3febfbff 00000000 00000000 00000000
CPU:     After generic, caps: 3febfbff 00000000 00000000 00000000
CPU:             Common caps: 3febfbff 00000000 00000000 00000000
CPU1: Intel(R) XEON(TM) CPU 2.20GHz stepping 04

Total of 2 processors activated (8703.18 BogoMIPS).
WARNING: No sibling found for CPU 0.
WARNING: No sibling found for CPU 1.
ENABLING IO-APIC IRQs
...changing IO-APIC physical APIC ID to 2 ... ok.
init IO_APIC IRQs
IO-APIC (apicid-pin) 2-0, 2-5, 2-9, 2-10, 2-11, 2-12, 2-20, 2-21, 2-22 not connected.
..TIMER: vector=0x31 pin1=2 pin2=0
number of MP IRQ sources: 18.
number of IO-APIC #2 registers: 24.
testing the IO APIC.......................

IO APIC #2......
.... register #00: 02000000
....... : physical APIC id: 02
.... register #01: 00178020
....... : max redirection entries: 0017
....... : IO APIC version: 0020
WARNING: unexpected IO-APIC, please mail
to [email protected]
WARNING: unexpected IO-APIC, please mail
to [email protected]
.... register #02: 00000000
....... : arbitration: 00
.... IRQ redirection table:
NR Log Phy Mask Trig IRR Pol Stat Dest Deli Vect:

 00 000 00  1    0    0   0   0    0    0    00
 01 003 03  0    0    0   0   0    1    1    39
 02 003 03  0    0    0   0   0    1    1    31
 03 003 03  0    0    0   0   0    1    1    41
 04 003 03  0    0    0   0   0    1    1    49
 05 000 00  1    0    0   0   0    0    0    00
 06 003 03  0    0    0   0   0    1    1    51
 07 003 03  0    0    0   0   0    1    1    59
 08 003 03  0    0    0   0   0    1    1    61
 09 000 00  1    0    0   0   0    0    0    00
 0a 000 00  1    0    0   0   0    0    0    00
 0b 000 00  1    0    0   0   0    0    0    00
 0c 000 00  1    0    0   0   0    0    0    00
 0d 003 03  0    0    0   0   0    1    1    69
 0e 003 03  0    0    0   0   0    1    1    71
 0f 003 03  0    0    0   0   0    1    1    79
 10 003 03  1    1    0   1   0    1    1    81
 11 003 03  1    1    0   1   0    1    1    89
 12 003 03  1    1    0   1   0    1    1    91
 13 003 03  1    1    0   1   0    1    1    99
 14 000 00  1    0    0   0   0    0    0    00
 15 000 00  1    0    0   0   0    0    0    00
 16 000 00  1    0    0   0   0    0    0    00
 17 003 03  1    1    0   1   0    1    1    A1

IRQ to pin mappings:
IRQ0 -> 0:2
IRQ1 -> 0:1
IRQ3 -> 0:3
IRQ4 -> 0:4
IRQ6 -> 0:6
IRQ7 -> 0:7
IRQ8 -> 0:8
IRQ13 -> 0:13
IRQ14 -> 0:14
IRQ15 -> 0:15
IRQ16 -> 0:16
IRQ17 -> 0:17
IRQ18 -> 0:18
IRQ19 -> 0:19
IRQ23 -> 0:23 .................................... done. Using local APIC timer interrupts. calibrating APIC timer ...
..... CPU clock speed is 2180.7314 MHz. ..... host bus clock speed is 99.1240 MHz.
cpu: 0, clocks: 991240, slice: 330413 CPU0<T0:991232,T1:660816,D:3,S:330413,C:991240>
cpu: 1, clocks: 991240, slice: 330413 CPU1<T0:991232,T1:330400,D:6,S:330413,C:991240> checking TSC synchronization across CPUs: passed.
mtrr: your CPUs had inconsistent fixed MTRR settings
mtrr: probably your BIOS does not setup all CPUs

with regards
Michael Arndt
[email protected]