Intel P6 vs P7 system call performance
Quoted 5 lines · Ingo Molnar
while reviewing the sysenter trampoline code i started wondering about the HT case. Dont HT boxes share the MSRs between logical CPUs? This pretty much breaks the concept of per-logical-CPU sysenter trampolines. It also makes context-switch time sysenter MSR writing impossible, so i really hope this is not the case.
Some MSRs are shared, some aren't. One must always check this in the IA32 Volume 3 manual. The three SYSENTER MSRs are not shared.
However, no-one has yet proven that writing to these in the context switch path has acceptable performance -- remember, there is _no_ a priori reason to assume _anything_ about performance on P4s, you really do need to measure things before taking design decisions.
Manfred had a version with fixed MSR values and the varying data in memory. Maybe that's actually faster.
Quoted 2 lines · Mikael Pettersson
Manfred had a version with fixed MSR values and the varying data in memory. Maybe that's actually faster.
The stack pointer is already changed on context switches since Ingo changed the kernel to use per-cpu TSS segments.
Manfred's code used a tiny stack (without a valid task struct, a different method of recovering than Linus' code). You can get that stack down to 6 words, (3 for debug trap, 3 more for nested NMI).
Combining these leads to an IMHO beautiful hack, which does work btw:
the 6 words fit into unused parts of the per-CPU TSS (just before tss->es). The MSR has a constant value:
wrmsr(MSR_IA32_SYSENTER_ESP, (u32) &tss->es, 0);
I found the fastest sysenter entry code looks like this:
sysenter_entry_point:
cld # Faster before sti.
sti # Re-enable interrupts after next insn.
movl -68(%esp),%esp # Load per-CPU stack from tss->esp0.
with appropriate fixups at the start of the NMI and debug trap handlers.
enjoy,
-- Jamie