irq handling code consolidation (i386)
RFC 1/1 irq handling code consolidation (i386)
i386 specific patch attached.
Signature · 2 lines
Andrey Panin | Embedded systems software developer [email protected] | PGP key: wwwkeys.pgp.net
arch/i386/Kconfig +4 -0
@@ -22,6 +22,10 @@ bool default y +config GENERIC_IRQ + bool + default y + config SBUS bool
arch/i386/kernel/irq.c +0 -370
391 lines not on this page · raw message
include/asm-i386/hw_irq.h +17 -0
@@ -140,4 +140,21 @@static inline void hw_resend_irq (struct hw_interrupt_type *h,unsigned int i) {}#endif +/* +* Currently unexpected vectors happen only on SMP and APIC. +* We _must_ ack these because every local APIC has only N +* irq slots per priority level, and a 'hanging, unacked' IRQ +* holds up an irq slot - in excessive cases (when multiple +* unexpected vectors occur) that might lock up the APIC +* completely. +*/ +#ifdef CONFIG_X86_LOCAL_APIC +#define ack_bad_irq (irq) ack_APIC_irq() +#else +#define ack_bad_irq (irq) do { } while (0) +#endif + +/* Return a pointer to the irq descriptor for IRQ. */ +#define irq_desc (irq) (irq_desc + (irq)) +#endif /* _ASM_HW_IRQ_H */
RFC 1/1 irq handling code consolidation (v850)
v850 specific patch attached. Not compiled, not tested.
Signature · 2 lines
Andrey Panin | Embedded systems software developer [email protected] | PGP key: wwwkeys.pgp.net
arch/v850/Kconfig +4 -0
@@ -23,6 +23,10 @@ bool default n +config CONFIG_GENERIC_IRQ + bool + default y + # Turn off some random 386 crap that can affect device config config ISA bool
arch/v850/kernel/irq.c +1 -347
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include/asm-v850/hw_irq.h +5 -0
@@ -5,4 +5,9 @@ { } +#define ack_bad_irq (irq) + +/* Return a pointer to the irq descriptor for IRQ. */ +#define irq_desc (irq) (irq_desc + (irq)) +#endif /* __V850_HW_IRQ_H__ */
RFC 1/1 irq handling code consolidation (x86_64)
In reply to Andrey Paninx86_64 specific patch attached. Not tested, not compiled.
Signature · 2 lines
Andrey Panin | Embedded systems software developer [email protected] | PGP key: wwwkeys.pgp.net
arch/x86_64/Kconfig +4 -0
@@ -25,6 +25,10 @@ 486, 586, Pentiums, and various instruction-set-compatible chips by AMD, Cyrix, and others. +config GENERIC_IRQ + bool + default y + config MMU bool default y
arch/x86_64/kernel/irq.c +0 -370
391 lines not on this page · raw message
include/asm-x86_64/hw_irq.h +17 -0
@@ -182,4 +182,21 @@#endif +/* +* Currently unexpected vectors happen only on SMP and APIC. +* We _must_ ack these because every local APIC has only N +* irq slots per priority level, and a 'hanging, unacked' IRQ +* holds up an irq slot - in excessive cases (when multiple +* unexpected vectors occur) that might lock up the APIC +* completely. +*/ +#ifdef CONFIG_X86_LOCAL_APIC +#define ack_bad_irq (irq) ack_APIC_irq() +#else +#define ack_bad_irq (irq) do { } while (0) +#endif + +/* Return a pointer to the irq descriptor for IRQ. */ +#define irq_desc (irq) (irq_desc + (irq)) +#endif /* _ASM_HW_IRQ_H */
RFC 1/1 irq handling code consolidation (alpha)
In reply to Andrey Paninalpha specific patch attached. Not tested, not compiled.
Signature · 2 lines
Andrey Panin | Embedded systems software developer [email protected] | PGP key: wwwkeys.pgp.net
arch/alpha/Kconfig +4 -0
@@ -20,6 +20,10 @@ bool default y +config GENERIC_IRQ + bool + default y + config UID16 bool
arch/alpha/kernel/irq.c +0 -281
293 lines not on this page · raw message
include/asm-alpha/hw_irq.h +5 -0
@@ -13,4 +13,9 @@#define ACTUAL_NR_IRQS NR_IRQS#endif +#define ack_bad_irq (irq) + +/* Return a pointer to the irq descriptor for IRQ. */ +#define irq_desc (irq) (irq_desc + (irq)) +#endif