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irq handling code consolidation, second try (x86_64 part)

RFC New Andrey Panin 1 participant 1 message Jan 4, 2003

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Andrey Panin

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RFC 1/1 irq handling code consolidation, second try (x86_64 part)

Hi all,

attached patch is a second try of IRQ handling code consolidation. This is a x86_64 specific patch (untested).

Best regards.

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Andrey Panin		| Embedded systems software developer
[email protected]	| PGP key: wwwkeys.pgp.net
arch/x86_64/Kconfig +4 -0
diff --minimal -urN -X /usr/share/dontdiff linux-2.5.53.vanilla/arch/x86_64/Kconfig linux-2.5.53/arch/x86_64/Kconfig
@@ -33,6 +33,10 @@
 	bool
 	default y
 
+config GENERIC_IRQ
+	bool
+	default y
+
 config ISA
 	bool
 	help
arch/x86_64/kernel/irq.c +0 -610

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include/asm-x86_64/hw_irq.h +27 -0
diff --minimal -urN -X /usr/share/dontdiff linux-2.5.53.vanilla/include/asm-x86_64/hw_irq.h linux-2.5.53/include/asm-x86_64/hw_irq.h
@@ -182,4 +182,31 @@
 
 #endif
 
+/*
+ * Currently unexpected vectors happen only on SMP and APIC.
+ * We _must_ ack these because every local APIC has only N
+ * irq slots per priority level, and a 'hanging, unacked' IRQ
+ * holds up an irq slot - in excessive cases (when multiple
+ * unexpected vectors occur) that might lock up the APIC
+ * completely.
+ */
+#ifdef CONFIG_X86_LOCAL_APIC
+#define arch_ack_bad_irq(irq) ack_APIC_irq()
+#else
+#define arch_ack_bad_irq(irq) do { } while (0)
+#endif
+
+/* Return a pointer to the irq descriptor for IRQ.  */
+#define irq_desc(irq) (irq_desc + (irq))
+
+/* Check irq number */
+#define arch_check_irq(irq) ((irq) >= NR_IRQS)
+
+/* Arch specific hook for setup_irq() */
+#define arch_setup_irq(irq, desc, irqaction) do { } while (0)
+
+/* Used in setup_irq() */
+#define ARCH_NONSHARED_IRQ_MASK \
+	~(IRQ_DISABLED | IRQ_AUTODETECT | IRQ_WAITING)
+
 #endif /* _ASM_HW_IRQ_H */