2.5 SYSENTER context-switch overhead on P4 :-(

I've measured the cost of the two wrmsr()'s added to the context-switch path to support SYSENTER in 2.5 kernels. Here's the data (clock cycles, averaged):

CPU wrmsr only only
type both cs esp
---- ---- --- ---
P4 2.4GHz (Xeon) 1722 860 863
P4 1.7GHz (Willamette) 1642 816 817
P3 800MHz (Coppermine) 158 76 76
P3 450MHz (Katmai) 216 105 105
P2 233MHz (Deschutes) 176 88 88
P2 233MHz (Klamath) 150 75 75

The other implementation with keeps the MSRs constant and uses a trampoline stack might be a better alternative.

/Mikael