u-boot-ptx-20030213-1
Hi,
on http://www.pengutronix.de/software/u-boot_en.html you'll find our latest u-boot patch, mostly for PXA250 and Cogent CSB226. It was made against current CVS, so be quick if you want to apply it ;-)
Most of the patch was already sent to Wolfgang in a more documented way, so this is mostly meant as something for people who actively develop for the PXA plattform.
Comments are welcome...
Robert
Signature · 5 lines
Dipl.-Ing. Robert Schwebel | http://www.pengutronix.de
Pengutronix - Linux Solutions for Science and Industry
Braunschweiger Str. 79, 31134 Hildesheim, Germany
Handelsregister: Amtsgericht Hildesheim, HRA 2686
Phone: +49-5121-28619-0 | Fax: +49-5121-28619-4Any chance of getting this into CVS ?
Quoted 1 line · Geir Thomassen
Any chance of getting this into CVS ?
You should be a little bit patient, Wolfgang has just moved office.
Robert
Signature · 5 lines
Dipl.-Ing. Robert Schwebel | http://www.pengutronix.de
Pengutronix - Linux Solutions for Science and Industry
Braunschweiger Str. 79, 31134 Hildesheim, Germany
Handelsregister: Amtsgericht Hildesheim, HRA 2686
Phone: +49-5121-28619-0 | Fax: +49-5121-28619-4Quoted 1 line · In message <[email protected]> you wrote:
Any chance of getting this into CVS ?
Yes, of course: it's in my queue, but it seems I won't find time for it for another week (until after the Embedded World).
Best regards,
Wolfgang Denk
Signature · 3 lines
Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd at denx.de See us @ Embedded World, Nuremberg, Feb 18-20, Hall 12.0 Booth 12-442
From your patch (memsetup.S, various versions ..)
/* Step 4f: Trigger a number (usually 8) refresh cycles by */
/* attempting non-burst read or write accesses to disabled */ /* SDRAM, as commonly specified in the power up sequence */ /* documented in SDRAM data sheets. The address(es) used */ /* for this purpose must not be cacheable. */
ldr r3, =CFG_DRAM_BASE
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]There should 9 writes, since the first write doesn't trigger a refresh cycle on PXA250. See Intel? PXA250 and PXA210 Processors Specification Update, Jan 2003, Errata #116, page 30.
.rept 9
str r2, [r2]
.endr
Signature · 1 line
Geir
Quoted 3 lines · Geir Thomassen
There should 9 writes, since the first write doesn't trigger a refresh cycle on PXA250. See Intel? PXA250 and PXA210 Processors Specification Update, Jan 2003, Errata #116, page 30.
Thanks, will be in the next patch.
Robert
Signature · 5 lines
Dipl.-Ing. Robert Schwebel | http://www.pengutronix.de
Pengutronix - Linux Solutions for Science and Industry
Braunschweiger Str. 79, 31134 Hildesheim, Germany
Handelsregister: Amtsgericht Hildesheim, HRA 2686
Phone: +49-5121-28619-0 | Fax: +49-5121-28619-4Quoted 3 lines · Robert Schwebel
Comments are welcome...
in cpu/xscale/start.S you do:
/* test if we run from flash or RAM - RAM/BDI: don't set cpuspeed */
/* FIXME: is the criterium used here only valid for PXA25X? */
mov r0, pc
and r0, r0, #0xF0000000 /* RAM is at 0xa0000000-0xafffffff */
subs r0, r0, #0xa0000000
beq setspeed_done mov r0, #2
mcr p14, 0, r0, c6, c0, 0setspeed_done:
Why? I can trace trough the CPU speed setting code without any trouble with a BDI, and I don't understand why there should be any problems doing so. Disabeling the CPU speed setting code without skipping the SDRAM init code at the same time might actually get you into other problems since the refresh periode of the SDRAM might be too long. Jumping over the SDRAM init is a very good idea, since the code is running from the SDRAM that the code is initializing. One important step of the init sequence is to disable the SDRAM.
Signature · 1 line
Geir
Quoted 14 lines · Geir Thomassen
in
cpu/xscale/start.Syou do:/* test if we run from flash or RAM - RAM/BDI: don't set cpuspeed */
/* FIXME: is the criterium used here only valid for PXA25X? */mov r0, pc and r0, r0, #0xF0000000 /* RAM is at 0xa0000000-0xafffffff */ subs r0, r0, #0xa0000000 beq setspeed_donemov r0, #2 mcr p14, 0, r0, c6, c0, 0
setspeed_done:
Quoted 8 lines
Why? I can trace trough the CPU speed setting code without any trouble with a BDI, and I don't understand why there should be any problems doing so. Disabeling the CPU speed setting code without skipping the SDRAM init code at the same time might actually get you into other problems since the refresh periode of the SDRAM might be too long. Jumping over the SDRAM init is a very good idea, since the code is running from the SDRAM that the code is initializing. One important step of the init sequence is to disable the SDRAM.
The code in question was added last week and I removed it today from my local tree :-)
The problem is that there is a bug in at least some hardware revisions of the PXA which in my case lets the debug handler disappear from the mini instruction cache once you access CP14 to switch the frequency. I've discussed this with the Abatron guys for some weeks now and they today have sent me a new firmware which works around the bug. It will be available officially in some days. However, as I'm now able to run the code in the debugger again the above code can be forgotten - I will not send it to Wolfgang officially.
Robert
Signature · 5 lines
Dipl.-Ing. Robert Schwebel | http://www.pengutronix.de
Pengutronix - Linux Solutions for Science and Industry
Braunschweiger Str. 79, 31134 Hildesheim, Germany
Handelsregister: Amtsgericht Hildesheim, HRA 2686
Phone: +49-5121-28619-0 | Fax: +49-5121-28619-4