Runtime memory barrier patching
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Quoted 8 lines · Linux Kernel Mailing List
ChangeSet 1.1169, 2003/04/21 16:23:20-07:00, [email protected]
[PATCH] Runtime memory barrier patching
This implements automatic code patching of memory barriers based on the CPU capabilities. Normally lock ; addl $0,(%esp) barriers are used, but these are a bit slow on the Pentium 4.
very nice. Question: would it be doable use this for prefetch() as well? Eg default to a non-prefetch kernel and patch in the proper prefetch instruction for the current cpu ? (eg AMD prefetch vs Intel one etc etc)
Quoted 5 lines · Arjan van de Ven
Quoted 4 lines · Linux Kernel Mailing List
ChangeSet 1.1169, 2003/04/21 16:23:20-07:00, [email protected]
[PATCH] Runtime memory barrier patching
Quoted 8 lines
Quoted 4 lines
This implements automatic code patching of memory barriers based on the CPU capabilities. Normally lock ; addl $0,(%esp) barriers are used, but these are a bit slow on the Pentium 4.
very nice. Question: would it be doable use this for
prefetch()as well? Eg default to a non-prefetch kernel and patch in the proper prefetch instruction for the current cpu ? (eg AMD prefetch vs Intel one etc etc)
Yes, I already implemented it, but have yet to boot it.
You only need Intel and AMD prefetch. For all Athlons the SSE prefetches work (because we force the SSE MSR bit to on). prefetchw is 3dnow. 3dnow non 'w' prefetches would only make sense on the K6, but they're not really worth it there because it doesn't have enough oustanding loads in the memory unit and worse prefetch is microcoded there.
-Andi
Quoted 2 lines · Andi Kleen
You only need Intel and AMD prefetch. For all Athlons the SSE prefetches work (because we force the SSE MSR bit to on).
Except those before Athlon XP which didn't have SSE.
Dave