cpufreq on Pentium M

DISCUSSION Matthew Miller 3 participants 3 messages Jun 13, 2003 4 messages not in the archive

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Matthew Miller

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2003-06-13 02:32 UTC #4 lore raw

Quoted 3 lines · Dave Jones

For info folks, I've now had a dozen or so mails with the same cache descriptors. Please don't send me any more centrino based outputs, I have plenty now, thanks 8-)

Hi Dave. This is the output from my Celeron 600A system -- it's a tiny bit different from what others posted to the list (an 0x86 instead of an 0x87). My understanding is that this CPU has half the L2 cache of the "real" Pentium M. Hope this is helpful and not annoying. Also, a question: I had assumed that the lack of info in /proc/cpuinfo was simply that an informational problem, and that the cache is actually working. Am I mistaken? (I.e. will having the kernel support this be a huge performance increase?) Thanks!

/proc/cpuinfo:

processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 9
model name : Mobile Intel(R) Celeron(R) processor 600MHz
stepping : 5
cpu MHz : 595.408
cache size : 0 KB
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 2
wp : yes
flags : fpu vme de pse tsc msr mce cx8 sep mtrr pge mca cmov pat clflush dts acpi mmx fxsr sse sse2 tm
bogomips : 1186.20

x86info -c:

x86info v1.9. Dave Jones 2001, 2002
Feedback to <[email protected]>.

Found 1 CPU
Family: 6 Model: 9 Stepping: 5 Type: 0 [ Original OEM] unknown TLB/cache descriptor:

	0xb0
unknown TLB/cache descriptor:
	0xb3
Instruction TLB: 4MB pages, fully associative, 2 entries
unknown TLB/cache descriptor:
	0x86
unknown TLB/cache descriptor:
	0x30
Data TLB: 4MB pages, 4-way associative, 8 entries
unknown TLB/cache descriptor:
	0x2c

Signature · 2 lines

Matthew Miller           [email protected]        <http://www.mattdm.org/>
Boston University Linux      ------>                <http://linux.bu.edu/>

Dave Jones

2003-06-13 10:38 UTC #5 lore raw

Quoted 4 lines · Matthew Miller

Hi Dave. This is the output from my Celeron 600A system -- it's a tiny bit different from what others posted to the list (an 0x86 instead of an 0x87). My understanding is that this CPU has half the L2 cache of the "real" Pentium M. Hope this is helpful and not annoying.

Yeah, I'd realised that was also missing. I'll get it in sync with 2.5 after Marcelo makes a 2.4.21

Quoted 5 lines

Also, a question: I had
assumed that the lack of info in /proc/cpuinfo was simply that an informational problem, and that the cache is actually working. Am I mistaken? (I.e. will having the kernel support this be a huge performance increase?) Thanks!

performance-wise, it may make a small difference on SMP systems, as it affects the balancing of the scheduler. On UP, shouldn't be any difference.

Dave

Matthew Miller

2003-06-13 13:10 UTC #6 lore raw

Quoted 4 lines · Dave Jones

Quoted 2 lines
mistaken? (I.e. will having the kernel support this be a huge performance increase?) Thanks!
performance-wise, it may make a small difference on SMP systems, as it affects the balancing of the scheduler. On UP, shouldn't be any difference.

Ok, thanks. It's not an SMP subnotebook. :)

Signature · 2 lines

Matthew Miller           [email protected]        <http://www.mattdm.org/>
Boston University Linux      ------>                <http://linux.bu.edu/>