PCI MWI updates/fixes

PATCH New Jeff Garzik 1 participant 1 message Aug 31, 2003 PCI

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Jeff Garzik

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2003-08-31 03:00 UTC #0 lore raw

PATCH 1/1 PCI MWI updates/fixes

Marcelo, please do a

bk pull bk://kernel.bkbits.net/jgarzik/misc-2.4

This will update the following files:

 arch/i386/kernel/pci-i386.c  |   11 ++++++++
 arch/i386/kernel/pci-i386.h  |    2 +
 arch/i386/kernel/pci-pc.c    |    2 +
 arch/i386/kernel/pci-visws.c |    1 
 drivers/pci/pci.c            |   55 ++++++++++++++++++++++---------------------
 5 files changed, 45 insertions(+), 26 deletions(-)

through these ChangeSets:

<[email protected]> (03/08/30 1.1102)
[PCI] update Memory-Write-Invalidate (MWI) transaction support

Sync up PCI MWI code with 2.5:
- no changes required for drivers or architectures with HAVE_ARCH_PCI_MWI;
- do respect BIOS settings: if the cacheline size is multiple

     of that we have expected, assume that this is on purpose;

- assume cacheline size of 32 bytes for all x86s except K7/K8 and P4. Actually it's good for 386/486s as quite a few PCI devices do not support smaller values.

arch/i386/kernel/pci-i386.c +11 -0

diff -Nru a/arch/i386/kernel/pci-i386.c b/arch/i386/kernel/pci-i386.c
@@ -295,6 +295,17 @@
 	}
 }
 
+void __init pcibios_set_cacheline_size(void)
+{
+	struct cpuinfo_x86 *c = &boot_cpu_data;
+
+	pci_cache_line_size = 32 >> 2;
+	if (c->x86 >= 6 && c->x86_vendor == X86_VENDOR_AMD)
+		pci_cache_line_size = 64 >> 2;	/* K7 & K8 */
+	else if (c->x86 > 6)
+		pci_cache_line_size = 128 >> 2;	/* P4 */
+}
+
 void __init pcibios_resource_survey(void)
 {
 	DBG("PCI: Allocating resources\n");

arch/i386/kernel/pci-i386.h +2 -0

diff -Nru a/arch/i386/kernel/pci-i386.h b/arch/i386/kernel/pci-i386.h
@@ -27,8 +27,10 @@
 /* pci-i386.c */
 
 extern unsigned int pcibios_max_latency;
+extern u8 pci_cache_line_size;
 
 void pcibios_resource_survey(void);
+void pcibios_set_cacheline_size(void);
 int pcibios_enable_resources(struct pci_dev *, int);
 
 /* pci-pc.c */

arch/i386/kernel/pci-pc.c +2 -0

diff -Nru a/arch/i386/kernel/pci-pc.c b/arch/i386/kernel/pci-pc.c
@@ -1428,6 +1428,8 @@
 		return;
 	}
 
+	pcibios_set_cacheline_size();
+
 	printk(KERN_INFO "PCI: Probing PCI hardware\n");
 #ifdef CONFIG_ACPI_PCI
 	if (use_acpi_pci && !acpi_pci_irq_init()) {

arch/i386/kernel/pci-visws.c +1 -0

diff -Nru a/arch/i386/kernel/pci-visws.c b/arch/i386/kernel/pci-visws.c
@@ -119,6 +119,7 @@
 {
 	unsigned int sec_bus = li_pcib_read16(LI_PCI_BUSNUM) & 0xff;
 
+	pcibios_set_cacheline_size();
 	printk("PCI: Probing PCI hardware on host buses 00 and %02x\n", sec_bus);
 	pci_scan_bus(0, &visws_pci_ops, NULL);
 	pci_scan_bus(sec_bus, &visws_pci_ops, NULL);

drivers/pci/pci.c +29 ~~-26~~

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