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PATCH Andi Kleen 2 participants 5 messages Aug 13, 2004 1 message not in the archive

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Andi Kleen

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#1 lore raw

Review line 48

Quoted 9 lines · Paweâ Sikora

+++ linux-2.6.8-rc4/arch/i386/kernel/cpu/proc.c 2004-08-13 16:48:53.971370504 +0200

(quoted diff) +2 -2
@@ -44,8 +44,8 @@
 		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 
 		/* Intel-defined (#2) */
-		"pni", NULL, NULL, "monitor", "ds_cpl", NULL, NULL, "tm2",
-		"est", NULL, "cid", NULL, NULL, NULL, NULL, NULL,
+		"sse3", NULL, NULL, "monitor", "ds_cpl", NULL, NULL, "est",
+		"tm2", NULL, "cid", NULL, NULL, NULL, "xtpr", NULL,

You cannot just do the pni -> sse3 rename. That could break existing applications that read /proc/cpuinfo and parse it. The only way would be to add a new sse3 flag in addition to pni, but I guess that would be not worth the ugly special case.

-Andi

#2 lore raw
Quoted 5 lines · Andi Kleen
Quoted 4 lines · Paweâ Sikora

+++ linux-2.6.8-rc4/arch/i386/kernel/cpu/proc.c 2004-08-13
16:48:53.971370504 +0200 @@ -44,8 +44,8 @@
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

Quoted 10 lines

Review

Quoted 5 lines
(quoted diff) +2 -2
 		/* Intel-defined (#2) */
-		"pni", NULL, NULL, "monitor", "ds_cpl", NULL, NULL, "tm2",
-		"est", NULL, "cid", NULL, NULL, NULL, NULL, NULL,
+		"sse3", NULL, NULL, "monitor", "ds_cpl", NULL, NULL, "est",
+		"tm2", NULL, "cid", NULL, NULL, NULL, "xtpr", NULL,

You cannot just do the pni -> sse3 rename. That could break existing applications that read /proc/cpuinfo and parse it. The only way would be to add a new sse3 flag in addition to pni, but I guess that would be not worth the ugly special case.

Ok, it's now correct?

Signature · 3 lines
/* Copyright (C) 2003, SCO, Inc. This is valuable Intellectual Property. */

                           #define say(x) lie(x)

Index: 2.6.8-cpu_feature.patch
===================================================================
RCS file: /cvsroot/SOURCES/Attic/2.6.8-cpu_feature.patch,v retrieving revision 1.1.2.1

2.6.8-cpu_feature.patch +27 -2
diff -u -r1.1.2.1 2.6.8-cpu_feature.patch
@@ -6,7 +6,7 @@
  		/* Intel-defined (#2) */
 -		"pni", NULL, NULL, "monitor", "ds_cpl", NULL, NULL, "tm2",
 -		"est", NULL, "cid", NULL, NULL, NULL, NULL, NULL,
-+		"sse3", NULL, NULL, "monitor", "ds_cpl", NULL, NULL, "est",
++		"pni", NULL, NULL, "monitor", "ds_cpl", NULL, NULL, "est",
 +		"tm2", NULL, "cid", NULL, NULL, NULL, "xtpr", NULL,
  		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

@@ -19,7 +19,7 @@
  		/* Intel-defined (#2) */
 -		"pni", NULL, NULL, "monitor", "ds_cpl", NULL, NULL, "tm2",
 -		"est", NULL, "cid", NULL, NULL, "cmpxchg16b", NULL, NULL,
-+		"sse3", NULL, NULL, "monitor", "ds_cpl", NULL, NULL, "est",
++		"pni", NULL, NULL, "monitor", "ds_cpl", NULL, NULL, "est",
 +		"tm2", NULL, "cid", NULL, NULL, "cx16", "xtpr", NULL,
  		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

@@ -42,6 +42,22 @@
  
  /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
  #define X86_FEATURE_XSTORE	(5*32+ 2) /* on-CPU RNG present (xstore insn) */
+@@ -93,13 +97,14 @@
+ #define cpu_has_tsc		boot_cpu_has(X86_FEATURE_TSC)
+ #define cpu_has_pae		boot_cpu_has(X86_FEATURE_PAE)
+ #define cpu_has_pge		boot_cpu_has(X86_FEATURE_PGE)
+-#define cpu_has_sse2		boot_cpu_has(X86_FEATURE_XMM2)
+ #define cpu_has_apic		boot_cpu_has(X86_FEATURE_APIC)
+ #define cpu_has_sep		boot_cpu_has(X86_FEATURE_SEP)
+ #define cpu_has_mtrr		boot_cpu_has(X86_FEATURE_MTRR)
+ #define cpu_has_mmx		boot_cpu_has(X86_FEATURE_MMX)
+ #define cpu_has_fxsr		boot_cpu_has(X86_FEATURE_FXSR)
+ #define cpu_has_xmm		boot_cpu_has(X86_FEATURE_XMM)
++#define cpu_has_xmm2		boot_cpu_has(X86_FEATURE_XMM2)
++#define cpu_has_xmm3		boot_cpu_has(X86_FEATURE_XMM3)
+ #define cpu_has_ht		boot_cpu_has(X86_FEATURE_HT)
+ #define cpu_has_mp		boot_cpu_has(X86_FEATURE_MP)
+ #define cpu_has_nx		boot_cpu_has(X86_FEATURE_NX)
 --- linux-2.6.8-rc4/include/asm-x86_64/cpufeature.h.orig	2004-08-10 04:23:13.000000000 +0200
 +++ linux-2.6.8-rc4/include/asm-x86_64/cpufeature.h	2004-08-13 16:53:48.776553304 +0200
 @@ -63,8 +63,14 @@

@@ -60,3 +76,12 @@
  
  #define cpu_has(c, bit)                test_bit(bit, (c)->x86_capability)
  #define boot_cpu_has(bit)      test_bit(bit, boot_cpu_data.x86_capability)
+@@ -81,6 +87,8 @@
+ #define cpu_has_mmx            1
+ #define cpu_has_fxsr           1
+ #define cpu_has_xmm            1
++#define cpu_has_xmm2           1
++#define cpu_has_xmm3           boot_cpu_has(X86_FEATURE_XMM3)
+ #define cpu_has_ht             boot_cpu_has(X86_FEATURE_HT)
+ #define cpu_has_mp             1 /* XXX */
+ #define cpu_has_k6_mtrr        0
#3 lore raw
Quoted 1 line

Ok, it's now correct?

My english is poor :-(

Signature · 3 lines
/* Copyright (C) 2003, SCO, Inc. This is valuable Intellectual Property. */

                           #define say(x) lie(x)
author
#4 lore raw
In reply to Paweł Sikora
Quoted 17 lines · Pawe?? Sikora
Quoted 5 lines · Andi Kleen
Quoted 4 lines · Pawe? Sikora

+++ linux-2.6.8-rc4/arch/i386/kernel/cpu/proc.c 2004-08-13
16:48:53.971370504 +0200 @@ -44,8 +44,8 @@
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

Quoted 10 lines

Review

Quoted 5 lines
(quoted diff) +2 -2
 		/* Intel-defined (#2) */
-		"pni", NULL, NULL, "monitor", "ds_cpl", NULL, NULL, "tm2",
-		"est", NULL, "cid", NULL, NULL, NULL, NULL, NULL,
+		"sse3", NULL, NULL, "monitor", "ds_cpl", NULL, NULL, "est",
+		"tm2", NULL, "cid", NULL, NULL, NULL, "xtpr", NULL,

You cannot just do the pni -> sse3 rename. That could break existing applications that read /proc/cpuinfo and parse it. The only way would be to add a new sse3 flag in addition to pni, but I guess that would be not worth the ugly special case.

Quoted 1 line

Ok, it's now correct?

Can you please send a new diff, a diff of a diff is not very nice to read.

-Andi

#5 lore raw
arch/i386/kernel/cpu/proc.c renamed from arch/i386/kernel/cpu/proc.c.orig +2 -2
@@ -44,8 +44,8 @@
 		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 
 		/* Intel-defined (#2) */
-		"pni", NULL, NULL, "monitor", "ds_cpl", NULL, NULL, "tm2",
-		"est", NULL, "cid", NULL, NULL, NULL, NULL, NULL,
+		"pni", NULL, NULL, "monitor", "ds_cpl", NULL, NULL, "est",
+		"tm2", NULL, "cid", NULL, NULL, NULL, "xtpr", NULL,
 		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
arch/x86_64/kernel/setup.c renamed from arch/x86_64/kernel/setup.c.orig +2 -2
@@ -1042,8 +1042,8 @@
 		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 
 		/* Intel-defined (#2) */
-		"pni", NULL, NULL, "monitor", "ds_cpl", NULL, NULL, "tm2",
-		"est", NULL, "cid", NULL, NULL, "cmpxchg16b", NULL, NULL,
+		"pni", NULL, NULL, "monitor", "ds_cpl", NULL, NULL, "est",
+		"tm2", NULL, "cid", NULL, NULL, "cx16", "xtpr", NULL,
 		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 	};
include/asm-i386/cpufeature.h renamed from include/asm-i386/cpufeature.h.orig +8 -3
@@ -71,9 +71,13 @@
 #define X86_FEATURE_P4		(3*32+ 7) /* P4 */
 
 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
-#define X86_FEATURE_EST		(4*32+ 7) /* Enhanced SpeedStep */
+#define X86_FEATURE_XMM3	(4*32+ 0) /* Streaming SIMD Extensions-3 */
 #define X86_FEATURE_MWAIT	(4*32+ 3) /* Monitor/Mwait support */
-
+#define X86_FEATURE_DSCPL	(4*32+ 4) /* CPL Qualified Debug Store */
+#define X86_FEATURE_EST		(4*32+ 7) /* Enhanced SpeedStep */
+#define X86_FEATURE_TM2		(4*32+ 8) /* Thermal Monitor 2 */
+#define X86_FEATURE_CID		(4*32+10) /* Context ID */
+#define X86_FEATURE_XTPR	(4*32+14) /* Send Task Priority Messages */
 
 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
 #define X86_FEATURE_XSTORE	(5*32+ 2) /* on-CPU RNG present (xstore insn) */

@@ -93,13 +97,14 @@
 #define cpu_has_tsc		boot_cpu_has(X86_FEATURE_TSC)
 #define cpu_has_pae		boot_cpu_has(X86_FEATURE_PAE)
 #define cpu_has_pge		boot_cpu_has(X86_FEATURE_PGE)
-#define cpu_has_sse2		boot_cpu_has(X86_FEATURE_XMM2)
 #define cpu_has_apic		boot_cpu_has(X86_FEATURE_APIC)
 #define cpu_has_sep		boot_cpu_has(X86_FEATURE_SEP)
 #define cpu_has_mtrr		boot_cpu_has(X86_FEATURE_MTRR)
 #define cpu_has_mmx		boot_cpu_has(X86_FEATURE_MMX)
 #define cpu_has_fxsr		boot_cpu_has(X86_FEATURE_FXSR)
 #define cpu_has_xmm		boot_cpu_has(X86_FEATURE_XMM)
+#define cpu_has_xmm2		boot_cpu_has(X86_FEATURE_XMM2)
+#define cpu_has_xmm3		boot_cpu_has(X86_FEATURE_XMM3)
 #define cpu_has_ht		boot_cpu_has(X86_FEATURE_HT)
 #define cpu_has_mp		boot_cpu_has(X86_FEATURE_MP)
 #define cpu_has_nx		boot_cpu_has(X86_FEATURE_NX)
include/asm-x86_64/cpufeature.h renamed from include/asm-x86_64/cpufeature.h.orig +9 -1
@@ -63,8 +63,14 @@
 #define X86_FEATURE_K8_C	(3*32+ 4) /* C stepping K8 */
 
 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
-#define X86_FEATURE_EST		(4*32+ 7) /* Enhanced SpeedStep */
+#define X86_FEATURE_XMM3	(4*32+ 0) /* Streaming SIMD Extensions-3 */
 #define X86_FEATURE_MWAIT	(4*32+ 3) /* Monitor/Mwait support */
+#define X86_FEATURE_DSCPL	(4*32+ 4) /* CPL Qualified Debug Store */
+#define X86_FEATURE_EST		(4*32+ 7) /* Enhanced SpeedStep */
+#define X86_FEATURE_TM2		(4*32+ 8) /* Thermal Monitor 2 */
+#define X86_FEATURE_CID		(4*32+10) /* Context ID */
+#define X86_FEATURE_CX16	(4*32+13) /* CMPXCHG16B */
+#define X86_FEATURE_XTPR	(4*32+14) /* Send Task Priority Messages */
 
 #define cpu_has(c, bit)                test_bit(bit, (c)->x86_capability)
 #define boot_cpu_has(bit)      test_bit(bit, boot_cpu_data.x86_capability)

@@ -81,6 +87,8 @@
 #define cpu_has_mmx            1
 #define cpu_has_fxsr           1
 #define cpu_has_xmm            1
+#define cpu_has_xmm2           1
+#define cpu_has_xmm3           boot_cpu_has(X86_FEATURE_XMM3)
 #define cpu_has_ht             boot_cpu_has(X86_FEATURE_HT)
 #define cpu_has_mp             1 /* XXX */
 #define cpu_has_k6_mtrr        0