change pagevec counters back to unsigned long and cacheline align

Change pagevec "nr" and "cold" back to "unsigned long", because 4 byte accesses can be slow on architectures < Pentium III (additional "data16" operand on instruction).

This still honours the cacheline alignment, making the size of "pagevec" structure a power of two (either 64 or 128 bytes).

Haven't been able to see any significant change on performance on my limited testing.

@@ -5,14 +5,15 @@
  * pages.  A pagevec is a multipage container which is used for that.
  */
 
-#define PAGEVEC_SIZE	15
+/* 14 pointers + two long's align the pagevec structure to a power of two */
+#define PAGEVEC_SIZE	14
 
 struct page;
 struct address_space;
 
 struct pagevec {
-	unsigned short nr;
-	unsigned short cold;
+	unsigned long nr;
+	unsigned long cold;
 	struct page *pages[PAGEVEC_SIZE];
 };
 

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