- Update asm-ia64/sn/sn_cpuid.h macros

@@ -79,7 +79,7 @@ static void sn_ack_irq(unsigned int irq)
 	int nasid;
 
 	irq = irq & 0xff;
-	nasid = smp_physical_node_id();
+	nasid = get_nasid();
 	event_occurred  	    HUB_L((uint64_t *) GLOBAL_MMR_ADDR(nasid, SH_EVENT_OCCURRED));
 	if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) {

@@ -109,7 +109,7 @@ static void sn_end_irq(unsigned int irq)
 
 	ivec = irq & 0xff;
 	if (ivec = SGI_UART_VECTOR) {
-		nasid = smp_physical_node_id();
+		nasid = get_nasid();
 		event_occurred = HUB_L((uint64_t *) GLOBAL_MMR_ADDR
 				       (nasid, SH_EVENT_OCCURRED));
 		/* If the UART bit is set here, we may have received an 

@@ -141,8 +141,8 @@ static void sn_set_affinity_irq(unsigned
 
 	cpuid = first_cpu(mask);
 	cpuphys = cpu_physical_id(cpuid);
-	t_nasid = cpu_physical_id_to_nasid(cpuphys);
-	t_slice = cpu_physical_id_to_slice(cpuphys);
+	t_nasid = cpuid_to_nasid(cpuid);
+	t_slice = cpuid_to_slice(cpuid);
 
 	while (sn_irq_info) {
 		int status;

98 lines not on this page · raw message

@@ -32,6 +32,7 @@
 #include <asm/hw_irq.h>
 #include <asm/current.h>
 #include <asm/sn/sn_cpuid.h>
+#include <asm/sn/sn_sal.h>
 #include <asm/sn/addrs.h>
 #include <asm/sn/shub_mmr.h>
 #include <asm/sn/nodepda.h>

@@ -136,7 +137,7 @@ sn2_global_tlb_purge(unsigned long start
 	ptc0 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH_PTC_0);
 	ptc1 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH_PTC_1);
 
-	mynasid = smp_physical_node_id();
+	mynasid = get_nasid();
 
 	spin_lock_irqsave(&sn2_global_ptc_lock, flags);
 

@@ -205,6 +206,7 @@ void sn2_ptc_deadlock_recovery(unsigned 
 
 /**
  * sn_send_IPI_phys - send an IPI to a Nasid and slice
+ * @nasid: nasid to receive the interrupt (may be outside partition)
  * @physid: physical cpuid to receive the interrupt.
  * @vector: command to send
  * @delivery_mode: delivery mechanism

@@ -219,15 +221,12 @@ void sn2_ptc_deadlock_recovery(unsigned 
  * %IA64_IPI_DM_NMI - pend an NMI
  * %IA64_IPI_DM_INIT - pend an INIT interrupt
  */
-void sn_send_IPI_phys(long physid, int vector, int delivery_mode)
+void sn_send_IPI_phys(int nasid, long physid, int vector, int delivery_mode)
 {
-	long nasid, slice, val;
+	long val;
 	unsigned long flags = 0;
 	volatile long *p;
 
-	nasid = cpu_physical_id_to_nasid(physid);
-	slice = cpu_physical_id_to_slice(physid);
-
 	p = (long *)GLOBAL_MMR_PHYS_ADDR(nasid, SH_IPI_INT);
 	val = (1UL << SH_IPI_INT_SEND_SHFT) |
 	    (physid << SH_IPI_INT_PID_SHFT) |

@@ -268,8 +267,14 @@ EXPORT_SYMBOL(sn_send_IPI_phys);
 void sn2_send_IPI(int cpuid, int vector, int delivery_mode, int redirect)
 {
 	long physid;
+	int nasid;
 
 	physid = cpu_physical_id(cpuid);
+	nasid = cpuid_to_nasid(cpuid);
+
+	/* the following is used only when starting cpus at boot time */
+	if (unlikely(nasid = -1))
+		ia64_sn_get_sapic_info(physid, &nasid, NULL, NULL);
 
-	sn_send_IPI_phys(physid, vector, delivery_mode);
+	sn_send_IPI_phys(nasid, physid, vector, delivery_mode);
 }

@@ -80,7 +80,8 @@ static int sn_force_interrupt_open(struc
 
 static int coherence_id_show(struct seq_file *s, void *p)
 {
-	seq_printf(s, "%d\n", cpuid_to_coherence_id(smp_processor_id()));
+	seq_printf(s, "%d\n", partition_coherence_id());
+
 	return 0;
 }
 

157 lines not on this page · raw message

@@ -43,7 +43,7 @@ struct sn_irq_info {
 	int		irq_share_cnt;	/* num devices sharing IRQ   */
 };
 
-extern void sn_send_IPI_phys(long, int, int);
+extern void sn_send_IPI_phys(int, long, int, int);
 
 #define CPU_VECTOR_TO_IRQ(cpuid,vector) (vector)
 

@@ -30,6 +30,12 @@
  * This structure provides a convenient way of keeping together 
  * all per-node data structures. 
  */
+struct phys_cpuid {
+	short			nasid;
+	char			subnode;
+	char			slice;
+};
+
 struct nodepda_s {
 	void 		*pdinfo;	/* Platform-dependent per-node info */
 	spinlock_t		bist_lock;

@@ -46,6 +52,10 @@ struct nodepda_s {
 	 */
 	struct nodepda_s	*pernode_pdaindr[MAX_COMPACT_NODES]; 
 
+	/*
+	 * Array of physical cpu identifiers. Indexed by cpuid.
+	 */
+	struct phys_cpuid	phys_cpuid[NR_CPUS];
 };
 
 typedef struct nodepda_s nodepda_t;

@@ -31,6 +31,7 @@
 #define  SN_SAL_NO_FAULT_ZONE_VIRTUAL		   0x02000010
 #define  SN_SAL_NO_FAULT_ZONE_PHYSICAL		   0x02000011
 #define  SN_SAL_PRINT_ERROR			   0x02000012
+#define  SN_SAL_GET_SAPIC_INFO                     0x02009999	//ZZZZ fix
 #define  SN_SAL_SET_ERROR_HANDLING_FEATURES	   0x0200001a	// reentrant
 #define  SN_SAL_GET_FIT_COMPT			   0x0200001b	// reentrant
 #define  SN_SAL_CONSOLE_PUTC                       0x02000021

@@ -843,6 +844,37 @@ ia64_sn_irtr_init(nasid_t nasid, void *b
 	return (int) rv.status;
 }
 
+/*
+ * Returns the nasid, subnode & slice corresponding to a SAPIC ID
+ */
+static inline u64
+ia64_sn_get_sapic_info(int sapicid, int *nasid, int *subnode, int *slice)
+{
+	struct ia64_sal_retval ret_stuff;
+
+	ret_stuff.status = 0;
+	ret_stuff.v0 = 0;
+	ret_stuff.v1 = 0;
+	ret_stuff.v2 = 0;
+	SAL_CALL_NOLOCK(ret_stuff, SN_SAL_GET_SAPIC_INFO, sapicid, 0, 0, 0, 0, 0, 0);
+
+/***** BEGIN HACK - temp til new proms available ********/
+	if (ret_stuff.status = SALRET_NOT_IMPLEMENTED) {
+		if (nasid) *nasid = sapicid & 0xfff;
+		if (subnode) *subnode = (sapicid >> 13) & 1;
+		if (slice) *slice = (sapicid >> 12) & 3;
+		return 0;
+	}
+/***** END HACK *******/
+
+	if (ret_stuff.status < 0)
+		return ret_stuff.status;
+
+	if (nasid) *nasid = (int) ret_stuff.v0;
+	if (subnode) *subnode = (int) ret_stuff.v1;
+	if (slice) *slice = (int) ret_stuff.v2;
+	return 0;
+}
 /*
  * This is the access point to the Altix PROM hardware performance
  * and status monitoring interface. For info on using this, see

diff -Naurp linux_base/arch/ia64/sn/kernel/iomv.c linux/arch/ia64/sn/kernel/iomv.c
@@ -9,6 +9,7 @@
 #include <linux/module.h>
 #include <asm/io.h>
 #include <asm/delay.h>
+#include <asm/sn/nodepda.h>
 #include <asm/sn/simulator.h>
 #include <asm/sn/pda.h>
 #include <asm/sn/sn_cpuid.h>