Serial 8250 OMAP support, take 2

PATCH In review Tony Lindgren 2 participants 4 messages Oct 28, 2004 – Oct 30, 2004 TTY layer and serial drivers

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Tony Lindgren

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2004-10-28 19:18 UTC #0 lore raw

PATCH 1/1 Serial 8250 OMAP support, take 2

Hi Andrew & Russell,

Here's an updated version of an earlier patch [1] to add OMAP support to the serial 8250 driver.

The new patch has been updated to use early_serial_setup() instead of register_serial(). This leaves out the earlier additional patch needed to serial_core.c [2], which caused a problem on PCI modems [3].

[1] http://lkml.org/lkml/2004/8/16/119
[2] http://lkml.org/lkml/2004/8/16/114
[3] http://bugme.osdl.org/show_bug.cgi?id=3312

Signed-off-by Tony Lindgren <[email protected]>

Regards,

Tony

drivers/serial/8250.c +42 -0

@@ -260,6 +260,15 @@
 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 		.flags		= UART_CAP_FIFO,
 	},
+	[PORT_OMAP] = {
+		.name		= "OMAP",
+		.fifo_size	= 64,
+		.tx_loadsz	= 64,
+		.fcr		= UART_FCR_ENABLE_FIFO |
+				  UART_FCR7_T_TRIGGER_56 |
+				  UART_FCR7_R_TRIGGER_60,
+		.flags		= UART_CAP_FIFO,
+	},
 };
 
 static _INLINE_ unsigned int serial_in(struct uart_8250_port *up, int offset)

@@ -1370,6 +1379,28 @@
 		serial_outp(up, UART_LCR, 0);
 	}
 
+#ifdef CONFIG_ARCH_OMAP
+	if (up->port.type == PORT_OMAP) {
+                serial_outp(up, UART_OMAP_MDR1, 0x07); /* disable UART */
+                serial_outp(up, UART_LCR, 0xBF);       /* select EFR */
+                serial_outp(up, UART_EFR, UART_EFR_ECB);
+                serial_outp(up, UART_LCR, UART_LCR_DLAB); /* set DLAB */
+                serial_outp(up, UART_DLL, 0x00);
+                serial_outp(up, UART_DLM, 0x00);
+                serial_outp(up, UART_LCR, 0x00);       /* reset DLAB */
+                serial_outp(up, UART_OMAP_SCR, 0x08);
+                serial_outp(up, UART_FCR, 0x00);
+                serial_outp(up, UART_MCR, 0x40);       /* enable TCR/TLR */
+                serial_outp(up, UART_TI752_TCR, 0x0F);
+                serial_outp(up, UART_TI752_TLR, 0x00);
+                serial_outp(up, UART_MCR, 0x00);
+                serial_outp(up, UART_LCR, 0xBF);       /* select EFR */
+                serial_outp(up, UART_EFR, 0x00);
+                serial_outp(up, UART_LCR, 0x00);       /* reset DLAB */
+                serial_outp(up, UART_OMAP_MDR1, 0x00); /* enable UART */
+        }
+#endif
+
 #ifdef CONFIG_SERIAL_8250_RSA
 	/*
 	 * If this is an RSA port, see if we can kick it up to the

@@ -1689,6 +1720,17 @@
 		serial_outp(up, UART_EFR, efr);
 	}
 
+#ifdef CONFIG_ARCH_OMAP1510
+	/* Workaround is needed to enable 115200 baud on OMAP1510 */
+        if (up->port.type == PORT_OMAP && cpu_is_omap1510()) {
+		if (baud == 115200) {
+			quot = 1;
+			serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
+		} else
+			serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
+        }
+#endif
+
 	if (up->capabilities & UART_NATSEMI) {
 		/* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
 		serial_outp(up, UART_LCR, 0xe0);

include/linux/serial_core.h +2 -1

@@ -37,7 +37,8 @@
 #define PORT_RSA	13
 #define PORT_NS16550A	14
 #define PORT_XSCALE	15
-#define PORT_MAX_8250	15	/* max port ID */
+#define PORT_OMAP	16
+#define PORT_MAX_8250	16	/* max port ID */
 
 /*
  * ARM specific type numbers.  These are not currently guaranteed

include/linux/serial_reg.h +23 -0

@@ -79,6 +79,15 @@
 #define UART_FCR6_T_TRIGGER_8	0x10 /* Mask for transmit trigger set at 8 */
 #define UART_FCR6_T_TRIGGER_24  0x20 /* Mask for transmit trigger set at 24 */
 #define UART_FCR6_T_TRIGGER_30	0x30 /* Mask for transmit trigger set at 30 */
+/* 16C752 definitions */
+#define UART_FCR7_R_TRIGGER_8	0x00 /* Mask for receive trigger set at 8 */
+#define UART_FCR7_R_TRIGGER_16	0x40 /* Mask for receive trigger set at 16 */
+#define UART_FCR7_R_TRIGGER_56	0x80 /* Mask for receive trigger set at 56 */
+#define UART_FCR7_R_TRIGGER_60	0xC0 /* Mask for receive trigger set at 60 */
+#define UART_FCR7_T_TRIGGER_8	0x00 /* Mask for transmit trigger set at 8 */
+#define UART_FCR7_T_TRIGGER_16	0x10 /* Mask for transmit trigger set at 16 */
+#define UART_FCR7_T_TRIGGER_32	0x20 /* Mask for transmit trigger set at 32 */
+#define UART_FCR7_T_TRIGGER_56	0x30 /* Mask for transmit trigger set at 56 */
 #define UART_FCR7_64BYTE	0x20 /* Go into 64 byte mode (TI16C750) */
 
 #define UART_LCR	3	/* Out: Line Control Register */

@@ -307,5 +316,19 @@
 #define SERIAL_RSA_BAUD_BASE (921600)
 #define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)
 
+/*
+ * Extra serial register definitions for the internal UARTs 
+ * in TI OMAP processors.
+ */
+#define UART_OMAP_MDR1		0x08	/* Mode definition register */
+#define UART_OMAP_MDR2		0x09	/* Mode definition register 2 */
+#define UART_OMAP_SCR		0x10	/* Supplementary control register */
+#define UART_OMAP_SSR		0x11	/* Supplementary status register */
+#define UART_OMAP_EBLR		0x12	/* BOF length register */
+#define UART_OMAP_OSC_12M_SEL	0x13	/* OMAP1510 12MHz osc select */
+#define UART_OMAP_MVER		0x14	/* Module version register */
+#define UART_OMAP_SYSC		0x15	/* System configuration register */
+#define UART_OMAP_SYSS		0x16	/* System status register */
+
 #endif /* _LINUX_SERIAL_REG_H */

Russell King

2004-10-28 19:33 UTC #1 lore raw

Quoted 6 lines · Tony Lindgren

Here's an updated version of an earlier patch [1] to add OMAP support to the serial 8250 driver.
The new patch has been updated to use early_serial_setup() instead of register_serial(). This leaves out the earlier additional patch needed to serial_core.c [2], which caused a problem on PCI modems [3].

One of the things which previous changes have done is to move us away from "port types" towards "capabilities" for serial ports, so things like the FIFO, hardware flow control and so forth can be individually controlled, rather than having to rely on a table of features.

So, it appears that OMAP ports are like a TI752 port, but with a couple of extra features. Can we use the existing TI75x feature support code for these ports?

Also, these ports seem to use extra address space which isn't covered by a request_region/request_mem_region... that's something which should be fixed.

Quoted 5 lines

include/linux/serial_reg.h +0 -0

@@ -79,6 +79,15 @@
 #define UART_FCR6_T_TRIGGER_8	0x10 /* Mask for transmit trigger set at 8 */
 #define UART_FCR6_T_TRIGGER_24  0x20 /* Mask for transmit trigger set at 24 */

include/linux/serial_reg.h line 90

Quoted 10 lines

include/linux/serial_reg.h +9 -0

 #define UART_FCR6_T_TRIGGER_30	0x30 /* Mask for transmit trigger set at 30 */
+/* 16C752 definitions */
+#define UART_FCR7_R_TRIGGER_8	0x00 /* Mask for receive trigger set at 8 */
+#define UART_FCR7_R_TRIGGER_16	0x40 /* Mask for receive trigger set at 16 */
+#define UART_FCR7_R_TRIGGER_56	0x80 /* Mask for receive trigger set at 56 */
+#define UART_FCR7_R_TRIGGER_60	0xC0 /* Mask for receive trigger set at 60 */
+#define UART_FCR7_T_TRIGGER_8	0x00 /* Mask for transmit trigger set at 8 */
+#define UART_FCR7_T_TRIGGER_16	0x10 /* Mask for transmit trigger set at 16 */
+#define UART_FCR7_T_TRIGGER_32	0x20 /* Mask for transmit trigger set at 32 */
+#define UART_FCR7_T_TRIGGER_56	0x30 /* Mask for transmit trigger set at 56 */

The set of UART_FCR6_xxx definitions are only left here for compatibility - there are others which use this file. Because the trigger levels is very dependent on the chip and sometimes which other features are enabled, I decided to provide new definitions:

#define UART_FCR_R_TRIG_00      0x00
#define UART_FCR_R_TRIG_01      0x40
#define UART_FCR_R_TRIG_10      0x80
#define UART_FCR_R_TRIG_11      0xc0
#define UART_FCR_T_TRIG_00      0x00
#define UART_FCR_T_TRIG_01      0x10
#define UART_FCR_T_TRIG_10      0x20
#define UART_FCR_T_TRIG_11      0x30

with a table above which detail their effects. I think it's silly creating lots of definitions for these bits, and then ending up with lots of macros definiting the same sort of thing. Please use the above only.

Signature · 4 lines

Russell King
 Linux kernel    2.6 ARM Linux   - http://www.arm.linux.org.uk/
 maintainer of:  2.6 PCMCIA      - http://pcmcia.arm.linux.org.uk/
                 2.6 Serial core

Tony Lindgren

author

2004-10-28 19:58 UTC #2 lore raw

Quoted 9 lines · Russell King

One of the things which previous changes have done is to move us away from "port types" towards "capabilities" for serial ports, so things like the FIFO, hardware flow control and so forth can be individually controlled, rather than having to rely on a table of features.
So, it appears that OMAP ports are like a TI752 port, but with a couple of extra features. Can we use the existing TI75x feature support code for these ports?

Well last time I checked at least the autoconfig failed. I can look into it a bit more.

Quoted 3 lines

Also, these ports seem to use extra address space which isn't covered by a request_region/request_mem_region... that's something which should be fixed.

OK, I'll change that.

Quoted 14 lines

The set of UART_FCR6_xxx definitions are only left here for compatibility - there are others which use this file. Because the trigger levels is very dependent on the chip and sometimes which other features are enabled, I decided to provide new definitions:
#define UART_FCR_R_TRIG_00      0x00
#define UART_FCR_R_TRIG_01      0x40
#define UART_FCR_R_TRIG_10      0x80
#define UART_FCR_R_TRIG_11      0xc0
#define UART_FCR_T_TRIG_00      0x00
#define UART_FCR_T_TRIG_01      0x10
#define UART_FCR_T_TRIG_10      0x20
#define UART_FCR_T_TRIG_11      0x30

Quoted 3 lines

with a table above which detail their effects. I think it's silly creating lots of definitions for these bits, and then ending up with lots of macros definiting the same sort of thing. Please use the above only.

OK, I'll change that too.

Tony

Tony Lindgren

author

2004-10-30 00:58 UTC #3 lore raw

Quoted 7 lines · Tony Lindgren

Quoted 6 lines · Russell King
One of the things which previous changes have done is to move us away from "port types" towards "capabilities" for serial ports, so things like the FIFO, hardware flow control and so forth can be individually controlled, rather than having to rely on a table of features.

Quoted 6 lines

Quoted 3 lines
So, it appears that OMAP ports are like a TI752 port, but with a couple of extra features. Can we use the existing TI75x feature support code for these ports?
Well last time I checked at least the autoconfig failed. I can look into it a bit more.

OK, got it working by resetting the ports before calling early_serial_setup(). The ports are now properly autodetected as PORT_16654, and seem to be working :) The new patch is quite minimal, see below!

Hmm, I wonder if there would be some advantage if the ports were detected as TI16750?

The omap specific reset function is basically:

omap_serial_outp(up, UART_OMAP_MDR1, 0x07); /* disable UART */ omap_serial_outp(up, UART_OMAP_MDR1, 0x00); /* enable UART */

Macro is_omap_port() is defined in the omap serial.h to check the port address. Moving that to somewhere else would allow removing one ifdef.

The macro cpu_is_omap1510() is omap specific, so one ifdef is still needed.

Quoted 5 lines

Quoted 3 lines
Also, these ports seem to use extra address space which isn't covered by a request_region/request_mem_region... that's something which should be fixed.
OK, I'll change that.

This is fixed now too.

Tony

drivers/serial/8250.c +16 -0

@@ -1689,6 +1689,17 @@
 		serial_outp(up, UART_EFR, efr);
 	}
 
+#ifdef CONFIG_ARCH_OMAP1510
+	/* Workaround to enable 115200 baud on OMAP1510 internal ports */
+	if (cpu_is_omap1510() && is_omap_port(up->port.membase)) {
+		if (baud == 115200) {
+			quot = 1;
+			serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
+		} else
+			serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
+        }
+#endif
+
 	if (up->capabilities & UART_NATSEMI) {
 		/* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
 		serial_outp(up, UART_LCR, 0xe0);

@@ -1742,6 +1753,11 @@
 	unsigned int size = 8 << up->port.regshift;
 	int ret = 0;
 
+#ifdef CONFIG_ARCH_OMAP
+	if (is_omap_port(up->port.membase))
+		size = 0x16 << up->port.regshift;
+#endif
+
 	switch (up->port.iotype) {
 	case UPIO_MEM:
 		if (up->port.mapbase) {

include/linux/serial_reg.h +14 -0

@@ -307,5 +307,19 @@
 #define SERIAL_RSA_BAUD_BASE (921600)
 #define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)
 
+/*
+ * Extra serial register definitions for the internal UARTs 
+ * in TI OMAP processors.
+ */
+#define UART_OMAP_MDR1		0x08	/* Mode definition register */
+#define UART_OMAP_MDR2		0x09	/* Mode definition register 2 */
+#define UART_OMAP_SCR		0x10	/* Supplementary control register */
+#define UART_OMAP_SSR		0x11	/* Supplementary status register */
+#define UART_OMAP_EBLR		0x12	/* BOF length register */
+#define UART_OMAP_OSC_12M_SEL	0x13	/* OMAP1510 12MHz osc select */
+#define UART_OMAP_MVER		0x14	/* Module version register */
+#define UART_OMAP_SYSC		0x15	/* System configuration register */
+#define UART_OMAP_SYSS		0x16	/* System status register */
+
 #endif /* _LINUX_SERIAL_REG_H */