Rm7000/Rm9000 cache code change for 64-bit

PATCH New Manish Lachwani 1 participant 1 message Nov 4, 2004 MIPS

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Manish Lachwani

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2004-11-04 18:04 UTC #0 lore raw

PATCH 1/1 Rm7000/Rm9000 cache code change for 64-bit

Hi Ralf

Attached small change fixes Rm7000/Rm9000 cache code to compile for 64-bit. This has been verified on the 2.6.10 kernel and tested on the Momentum Ocelot-3 board.

Please review

Thanks
Manish Lachwani

mips/mm/sc-rm7k.c renamed from mips/mm/sc-rm7k.c.orig +2 -2

@@ -127,13 +127,13 @@
 		      ".set mips0\n\t"
 		      ".set reorder"
 		      :
-		      : "r" (KSEG0ADDR(i)), "i" (Index_Store_Tag_SD));
+		      : "r" (CKSEG0ADDR(i)), "i" (Index_Store_Tag_SD));
 	}
 }
 
 static __init void rm7k_sc_enable(void)
 {
-	void (*func)(void) = (void *) KSEG1ADDR(&__rm7k_sc_enable);
+	void (*func)(void) = (void *) CKSEG1ADDR(&__rm7k_sc_enable);
 
 	if (read_c0_config() & 0x08)			/* CONF_SE */
 		return;