Centrino speedstep

Hi,

On my Acer Travelmate 4000WLMi, with various 2.6.9 and 2.6.10 kernels and patch sets, I keep getting the following message:

speedstep-centrino: invalid ACPI data
speedstep-centrino: no table support for CPU model "Intel(R) Pentium(R) M processor 1.50GHz":

(Some kernels report "Invalid control/status registers" instead of "invalid ACPI data").

My latest attempt was the stock 2.6.10 kernel, with ACPI patch set acpi-20041210-2.6.10-rc3.diff, and a fixed DSDT. Still no success.

Any help is appreciated.

Thanks,
Johan

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It looks like your notebook's BIOS does not report sufficient data to the speedstep-centrino cpufreq driver. Does the acpi-cpufreq driver work instead?

Dominik

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After looking the DSDT, this laptop do not support the _PDC switch, so the cpufreq-centrino driver will not work. But it should work with the acpi io driver though.

Interresting portion:

    OperationRegion (MNVS, SystemMemory, 0x1FEECE59, 0x60)
    Field (MNVS, AnyAcc, Lock, Preserve)
    {
        ...
        ...
        CLNM,   8,
        ...
    }

        Scope (_PR)
    {
        Processor (CPU0, 0x00, 0x00001010, 0x06)
        {
            Name (_PCT, Package (0x02)
            {
                ResourceTemplate ()
                {
                    Register (SystemIO, 0x08, 0x00, 0x00000000000000B2)
                },

                ResourceTemplate ()
                {
                    Register (SystemIO, 0x08, 0x00, 0x00000000000000B3)
                }
            })
            Method (_PSS, 0, NotSerialized)
            {
                If (CLNM)
                {
                    Return (CPSS)
                }

                Return (PPSS)
            }

            Name (CPSS, Package (0x01)
            {
                Package (0x06)
                {
                    0x0640,
                    0x5DC0,
                    0x0A,
                    0x0A,
                    0x89,
                    0x00
                }
            })
            Name (PPSS, Package (0x05)
            {
                ... (follow 5 packages defining the 5 P-states)
            }
            })
            Method (_PPC, 0, NotSerialized)
            {
                Return (0x00)
            }
        }

This also mean there is no way to get the ondemand governor (or any DVS requiring low latency driver) to work with this one (unless hardcoding a table in the cpufreq-centrino).

There is no _CST also, this means there is no C4 support :(

Bruno Ducrot

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This seems to be the case.

What exactly does that mean?

Would that be difficult to accomplish?

Nope. I'll have to do with C3...

BTW: To be able to compile my DSDT I needed some fixes, mostly trivial, except one: the final return value of Method(_STA) from Device(BAY1), around line 3222. Do you have any idea?

Thanks for helping,

Johan

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The latency in-between each P-state transitions is too high in order to use a dynamic voltage scaling algorithme to be practical. BTW, I am maybe wrong as stated by Dominik.

No.

Yes, though I'm not sure how to fix this correctly I'm afraid.

   4901                         Method (_STA, 0, NotSerialized)
   4902                         {
   4903                             If (\_SB.PCI0.IDE0.ESID)
   4904                             {
   4905                                 \_SB.PCI0.IDE0.SECN.CBAY ()
   4906                                 Store (^^BFLG, Local0)
   4907                                 If (LEqual (^^BNUM, 0x01))
   4908                                 {
   4909                                     If (And (Local0, 0x01))
   4910                                     {
   4911                                         If (\_SB.PCI0.LPC0.LV37)
   4912                                         {
   4913                                             Return (0x08)
   4914                                         }
   4915                                         Else
   4916                                         {
   4917                                             Return (0x0F)
   4918                                         }
   4919                                     }
                                           // this is the problem.  If
                                           // 'And (Local0, 0x01)' is
                                           // false.

                                           // Maybe adding this:
                                           Else
                                           {
                                               Return(8)
                                           }
                                           // will be ok.

   4920                                 }
   4921                                 Else
   4922                                 {
   4923                                     If (LEqual (^^BNUM, 0x02))
   4924                                     {
   4925                                         If (\_SB.PCI0.LPC0.LV37)
   4926                                         {
   4927                                             Return (0x08)
   4928                                         }
   4929                                         Else
   4930                                         {
   4931                                             Return (0x0F)
   4932                                         }
   4933                                     }
   4934                                     Else
   4935                                     {
   4936                                         Return (0x08)
   4937                                     }
   4938                                 }
   4939                             }
   4940                             Else
   4941                             {

4942 Return (0x08)
4943 }
4944 }

The trouble is that I'm not sure for the value of the return value, but I think this path is not taken anyway (BFLG will be equal to 1 if BNUM is 1 due to the CBAY() call).

Bruno Ducrot

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IIRC it depends on the latency reported by the ACPI data, and 100us (what I usually see there) isn't that bad...

Also no SSDT?

Dominik

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I don't trust the fact that having to go to SMI (with all the implied things like access to the SMRAM, flushing processor cache and so on) will give a latency of 100us, but of course I may be wrong.

Nope.

Bruno Ducrot

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sorry for interrupting thread flow, but I didn't understand this one...

I'm running on a tmate 4001 WLMi with speedstep-centrino driver and ondemand governor.

I don't see any problems... the clock scales correctly and fast... Is it possible to have a different DSDT from dominik's?

regards,
pedro venda.

Pedro João Lopes Venda
email: [email protected]
http://arrakis.dhis.org


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(The TravelMate is mine, Dominik analysed the DSDT for me.)

That's interesting to hear! I'd really love to give your DSTS a try (provided the experts can assure me that it will not blow up the notebook).

Can you send me your DSDT (via private mail, please)?

-- Johan

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That mean that intel have done a way to be pretty fast in order to put the processor in SMM. Interresting.

You must be sure that revision of the bios is the same, the 2 laptops are the exact same model, and there is the exact amount of memory.

Cheers,

Bruno Ducrot

--  Which is worse:  ignorance or apathy?
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mine has default memory:

2 infineon 256Mb DDR333 modules.

exact model is... how can I find it out?

regards,
pedro venda.

Pedro João Lopes Venda
email: [email protected]
http://arrakis.dhis.org


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sorry for the incoherence.

will dissassemble my dsdt tonight and upload it to somewhere on the internet.

are you completely unable to use speedstep-centrino and/or ondemand speedfreq governor?

regards,
pedro venda.

Pedro João Lopes Venda
email: [email protected]
http://arrakis.dhis.org


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here it is:
http://arrakis.dhis.org/linux/laptop/dsdt.dsl.gz

my bios version is:

System BIOS Ver: 3A06
VGA BIOS Ver: ATI-M11-008.018M.017.000
KBC Ver: PQ1A28

(may look like copied from your e-mail but wasn't)

the machines look exactly the same. the only difference is that mine works with the speedstep centrino driver and johan's doesn't.

This may be the responsible for mine to work with the speedstep driver:
(from kernel config)

      Default CPUFreq governor (ondemand)  --->
  x x              <M>   'performance' governor
  x x              <M>   'powersave' governor
  x x              <M>   'userspace' governor for userspace frequency scaling
  x x              [ ]     /proc/sys/cpu/ interface (2.4. / OLD)
  x x              ---   'ondemand' cpufreq policy governor
  x x              <*>   CPU frequency table helpers
  x x              ---   CPUFreq processor drivers
  x x              < > ACPI Processor P-States driver
  x x              < > AMD Mobile K6-2/K6-3 PowerNow!
  x x              < > AMD Mobile Athlon/Duron PowerNow!
  x x              < > AMD Opteron/Athlon64 PowerNow!
  x x              < > Cyrix MediaGX/NatSemi Geode Suspend Modulation
  x x              <M> Intel Enhanced SpeedStep
  x x              [*]   Use ACPI tables to decode valid frequency/voltage pairs
  x x              [*]   Built-in tables for Banias CPUs

the two last lines look to me like the tables referred above. am I right? Also, CPU frequency table helpers seems familiar. What are the differences between both tables really?

also, how exactly can I use ACPI throttling? because with the speestep driver, I can't go below 600MHz, but 12% of maximum frequency is 180MHz which I can reach using ACPI throttling.

care to comment?

I'm also using stock kernel 2.6.10 with stock acpi code but I have a different message:
speedstep-centrino: invalid ACPI data

But the module seems to work ok. is there an easy way to test it?

regards,
pedro venda.

Pedro João Lopes Venda
email: [email protected]
http://arrakis.dhis.org



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but throttling doesn't save you anything.

Dominik

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Do you have any idea of the actual power savings in relation to frequency scaling and sleep states? E.g., stepping down from 1.6Ghz to 800Mhz will save a lot (50%?), but how much is saved by using C3 state. More interesting, how much savings are lost by not being able to use C3 state?

-- Johan

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C0 C1 C2 C3
----------------------------------------------------------------------------------------------------------------
Intel Pentium(R) M Processor, 1400 MHz & 1.484V[19] 22 W 7.3 W 7.3 W 7.0 W/5.1 W/0.55W[**][20]

Intel Pentium(R) M Processor, 1400 MHz & 1.484V,
scaled down to 600 MHz 6 W 1.8 W 1.8 W 1.7 W/1.1 W/0.55W[**]

[**] first value: Sleep State; second value: Deep Sleep State; third value: Deeper Sleep State.

[19] Intel(R) Pentium(R) M Processor Datasheet, Order Nr. 252612, rev. 02, June 2003, p. 72.

[20] The extremely lower power consumption in Deeper Sleep and the fact that Deeper Sleep most commonly is only made available by the _CST method expresses the urgency needed in implementing it in the Linux kernel, and it has been merged into the latest 2.6.-sources for 2.6.11-rc1.

Dominik

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Thus wrote Dominik Brodowski:

Hmm, I always thought C3 implies at least Deep Sleep [*], at least for P4-M. Isn't that true for P-M?

[*] It is, AFAIR, possible to make C3 transition invoke Deeper Sleep.

Best regards,

Karol 'sziwan' Kozimor
sziwan-DETuoxkZsSqrDJvtcaxF/[email protected]


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Intel x86 and x86_64 Processors[15]

C1 - AutoHALT Power-Down state

C2 - Stop-Grant state

C3 - Sleep State

Deep Sleep State (normally used)

Deeper Sleep State (alternatively used, or available in
addition to Deep Sleep State)

[15] Data collected from Intel(R) 440BX AGPset: 82443BX Host Bridge/Controller Datasheet, Order Nr. 290633, rev. 01, April 1998, p. 4-31; Intel(R) 82801DBM I/O Controller Hub 4 Mobile (ICH4-M) Datasheet, Order Nr. 252337, rev. 01, January 2003, p. 362; Intel(R) Pentium(R) M Processor Datasheet, Order Nr. 252612, rev. 02, June 2003, pp. 11; and Intel(R) 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH) Datasheet, Order Nr. 252615, rev. 02, September 2003, p. 170.

:-)

Dominik

Well, it makes it run slightly cooler, so saves on fan power. Or am I mistaken?

Cheers,

Fred

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If there is indeed a correlation with the fan power, indeed. Usually this isn't the case, and then it doesn't matter at all.

Dominik

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How can it not be the case that there is correlation between the two? The processor produces heat (less if throttling down, right?) and the fan extracts heat from the inside of the machine.

Or there is something I'm utterly missing here (?).

Fred

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Yes.

Not necessarily. Only if the average CPU load would be higher than the rate the CPU is throttled to, i.e. if the CPU load is >= 100% for siginifcant amounts of time[*]. If not the CPU is put into the same hardware state ("idle state") because there is no work to do as if there were throttling, i.e. if "x" means the CPU has work to do, "i" means the CPU is in an idle mode, and "t" means the CPU is throttled, we see the following behaviour:

Much work to do:
-----------------------------------> time
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx (no throttling)
xxttxxttxxttxxttxxttxxttxxttxxttxxtt (throttling 50%)

(however, as the task now takes twice as long to complete, and the CPU still consumes power in "t", the CPU does consume more energy than if it weren't throttled. Only if the fan needs to run _because_ of the high CPU load and it consumes more power than the CPU in throttling mode, throttling may save energy.)

50% load average
xixixixixixixixixixixixixixixixixixi (no throttling)
xxttxxttxxttxxttxxttxxttxxttxxttxxtt (throttling 50%)
=> as the CPU is in the same hardware state on "i" or "t", no power
reduction is achieved because of throttling

10% load average
xiiiiiiiiixiiiiiiiiixiiiiiiiiixiiii (no throttling)
xittiittiittxittiittxittiittiittxit (throttling 50%)

	=> the same is true again ==> throttling doesn't save you anything

And as 100% CPU usage isn't that common on notebooks...

Dominik

[*] (>0.1/0.5s ?)

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I was missing something (brain power?). Very interesting. Thank you for that.

It is on mine... ;-).

Cheers,

Fred

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Actually you may save energy but only if you disable the L2 cache. I don't think people want that ;)

Bruno Ducrot

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Thus wrote Bruno Ducrot:

How is that? Could you elaborate?
Best regards,

Karol 'sziwan' Kozimor
sziwan-DETuoxkZsSqrDJvtcaxF/[email protected]


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If you disable L2 cache, then its no more true that the deadline of a given task is linear to the frequency due to memory bottleneck.

Bruno Ducrot

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Thus wrote Bruno Ducrot:

Ahh, this way around :) Yeah, I suppose nobody would want that :) Thanks,

Karol 'sziwan' Kozimor
sziwan-DETuoxkZsSqrDJvtcaxF/[email protected]


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It's non-intuitive since power consumption is an integral (i.e., the sum of individual power usage over time t). The area under the curve is what you care about.

For interactive use, the best scheduling algorithm for CPU idling is to run the CPU at 100% performance until there are no runnable tasks, then slam it to the lowest Cx state until woken by the next timer tick or interrupt. Since even slow C3 transitions on most platforms are 200 microseconds or less and given a HZ value of 1000, you still get 600 us of sleeping at C3 (3x the latency of a transition.) The longer-latency cpufreq transition is different, in that you should go to the lowest CPU state once you have M wakeups over N amount of time but only a small number of runnable tasks in that time period. Tune M and N based on the latency of cpufreq transitions for a platform.

With even speedstep transitions being less than a millisecond, there is no reason not to use it more.

Nate


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[Quoting Pedro Venda, on December 31 2004, 01:25, in "Re: Centrino speedst"]

Nope, my BIOS version is 3A08, not 3A06 ...
Bruno, does that mean that it's too risky to try?

I have looked on the Acer web site, but there are no BIOS upgrades for this model.

-- Johan

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[Quoting Johan Vromans, on December 31 2004, 10:31, in "Re: Centrino speedst"]

Don't bother, the DSDTs turn out to be identical anyway (except for the final argument of DefinitionBlock which is probably a serial number).

This increases the mystery why certain things do not work on my notebook while they do on Pedro's.

-- Johan

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[Quoting Pedro Venda, on December 31 2004, 01:25, in "Re: Centrino speedst"]

Hmm. You're using the standard 2.6.10 ACPI stuff, while I have applied the acpi patch kit. Could that be the difference?

-- Johan

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Will try it tomorrow, since tonight is a no-work night.

happy new year,

regards,
pedro venda.

Pedro João Lopes Venda
email: [email protected]
http://arrakis.dhis.org


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[Quoting Pedro Venda, on December 31 2004, 14:12, in "Re: [ACPI] Re: Centr"]

I've tried stock 2.6.10, and it makes no difference in my situation.

Happy new year, and take care!

-- Johan

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[Quoting Pedro Venda, on December 31 2004, 01:25, in "Re: Centrino speedst"]

Interesting. Neither stock 2.6.10 nor the acpi-patched version allows me to choose this governor. 'userspace' and 'ondemand' are the only possible options.

-- Johan

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When I wrote the e-mail, I made a mental note: explain the default governor option...

well, I forgot. It's my own patch.

regards,
pedro venda.

Pedro João Lopes Venda
email: [email protected]
http://arrakis.dhis.org


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The acpi-cpufreq driver loads, and the cpufreq tools seem to do something. But do they actually work? E.g. cpufreq-info reports that the limits are 1.6G - 600M, and cpufreq-set accepts 1.6G (confirmed by /proc/cpuinfo) but my CPU is only 1.5G...

-- Johan

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the same thing happen to my centrino, i have a 1.5g , and acpi-cpufreq set min 600 max 1.6G ... i manually echoed a new maximum of 1.5 ... the scaling seems to work fine, it automatically switch from 600 to 1500

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You should fix the DSDT and replace the frequency value of the P0 state with 1500 instead of 1600. Else frequency calculations in the kernel get mixed up which can cause too short or too long delays.

Dominik

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I've already fixed my DSDT to compile, so this would be easily added ... if I knew where. Can you point me in the right direction?

-- Johan

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in the _PSS, first block, somewhere should be 1600. Change it to 1500.

Dominik

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I see two places. Second is a PPSS block with 5 entries, corresponding to the CPU states. The first one contains a 0x640 (= 1600). Right before it is a CPSS block, that seems to be a copy of the first CPU state. I guess this has to be modified as well?

        Method(_PSS) {
            If(CLNM) {
                Return(CPSS)
            }
            Return(PPSS)
        }
        Name(CPSS, Package(0x1) {
            Package(0x6) {
==>             0x0640,
                0x5dc0,
                0xa,
                0xa,
                0x89,
                0x0,
            },
        })
        Name(PPSS, Package(0x5) {
            Package(0x6) {
==>             0x0640,
                0x5dc0,
                0xa,
                0xa,
                0x89,
                0x0,
            },
            ... 4 more for other states ...
       })

-- Johan

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Yes, indeed. These seem to be the right places for modification.

Dominik

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Okay, will do.

However, that brings up an interesting question: what guarantees that the figures in the tables match the actual capabilities of the CPU? Currently, it seems that my 1.5Ghz CPU is happily running at 1.6Ghz.

-- Johan

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Run "x86info --mhz" and you'll most probably see the CPU runs at 1.5GHz even though it is reported by ACPI as 1.6GHz.

Dominik

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Hmm. x86info doesn't seem to produce reliable figures:

  # cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq
  600000
  # x86info --mhz
  x86info v1.12b.  Dave Jones 2001-2003
  Feedback to <[email protected]>.

Found 1 CPU
--------------------------------------------------------------------------
unknown TLB/cache descriptor: 0xf0
unknown TLB/cache descriptor: 0x7d
Family: 6 Model: 13 Stepping: 6 Type: 0 Brand: 6 CPU Model: Unknown CPU Original OEM
Instruction TLB: 4K pages, 4-way associative, 128 entries. Data TLB: 4K pages, 4-way associative, 128 entries. Instruction TLB: 4MB pages, fully associative, 2 entries
unknown TLB/cache descriptor: 0xf0
unknown TLB/cache descriptor: 0x7d
L1 Instruction cache:
:Size 32KB 8-way associative.
line size=64 bytes.
Data TLB: 4MB pages, 4-way associative, 8 entries L1 Data cache:
Size: 32KB 8-way associative.
line size=64 bytes.
100MHz processor (estimate).

  # cat /proc/cpuinfo
  processor       : 0
  vendor_id       : GenuineIntel
  cpu family      : 6
  model           : 13
  model name      : Intel(R) Pentium(R) M processor 1.50GHz
  stepping        : 6
  cpu MHz         : 599.502
  cache size      : 2048 KB
  fdiv_bug        : no
  hlt_bug         : no
  f00f_bug        : no
  coma_bug        : no
  fpu             : yes
  fpu_exception   : yes
  cpuid level     : 2
  wp              : yes
  flags           : fpu vme de pse tsc msr mce cx8 sep mtrr pge mca cmov pat clflush dts acpi mmx fxsr sse sse2 ss tm pbe est tm2
  bogomips        : 1189.47

-- Johan

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C-States triggering... Problably keeping the CPU busy will allow to produce better results.

Dominik

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Its maybe possible to get MSR MSR_IA32_PERF_STATUS and decode it in userspace?

Cheers,

Bruno Ducrot

--  Which is worse:  ignorance or apathy?
--  Don't know.  Don't care.


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The decoding is already there in cpufrequtils//debug/i386/centrino-decode.c, someone just needs to adapt the MSR access as found in powernow-k8-decode.c in same directory :)

Dominik

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did those 2 changes fix your problems?
i have this problem too, and i "fixed" with echo a new max ... but now as suggested i'll fix the dsdt

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Yes, it now reports 1.5Ghz as the max speed, as it should.

-- Johan

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Using msr_is32_perf_status I found out that the actual frequencies are 1500, 1200, 1000, 800, 600 (Mhz). The original DSDT reports 1600, 1400, 1200, 800, 600.

Another typical DSDT brokenness?

-- Johan

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It definitely seems so.

Thanks,
Dominik

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a question.. how windows knows the maximum is 1500 insted of 1600?

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Could you send me the output of acpidmp, please ?

wget ftp://ftp.kernel.org//pub/linux/kernel/people/lenb/acpi/utils/pmtools-20031210.tar.bz2 tar xjvfp pmtools-20031210.tar.bz2
cd pmtools-20031210/acpidmp
make
sudo ./acpidmp > acpidmp.out
bzip2 acpidmp.out

Then mail me (privately) the acpidmp.out.bz2, or provide a link.

Cheers,

Bruno Ducrot

--  Which is worse:  ignorance or apathy?
--  Don't know.  Don't care.


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