Platform SMIs and their interferance with tsc based delay calibration
PATCH 1/1 Platform SMIs and their interferance with tsc based delay calibration
Missed copying to the list earlier... sorry if this mail is a duplicate.
Following up on earlier thread
http://www.ussg.iu.edu/hypermail/linux/kernel/0501.3/index.html#1694
Changes from the earlier version:
(1) Now this new routine is generic
(2) Handles both i386 amd x86-64
(3) Repeates the delay calibration 5 times to get good value
Thanks,
Venki
Issue:
Current tsc based delay_calibration can result in significant errors in loops_per_jiffy count when the platform events like SMIs
(System Management Interrupts that are non-maskable) are present. This could lead to potential kernel panic(). This issue is becoming more visible with 2.6 kernel (as default HZ is 1000) and on platforms with higher SMI handling latencies. During the boot time, SMIs are mostly used by BIOS (for things like legacy keyboard emulation).
Description:
The psuedocode for current delay calibration with tsc based delay looks like
(0) Estimate a value for loops_per_jiffy
(1) While (loops_per_jiffy estimate is accurate enough)
(2) wait for jiffy transition (jiffy1) (3) Note down current tsc (tsc1) (4) loop until tsc becomes tsc1 + loops_per_jiffy (5) check whether jiffy changed since jiffy1 or not and refine
loops_per_jiffy estimate
Consider the following cases
Case 1:
If SMIs happen between (2) and (3) above, we can end up with a loops_per_jiffy value that is too low. This results in shorted delays and kernel can panic () during boot (Mostly at IOAPIC timer initialization timer_irq_works() as we don't have enough timer interrupts in a specified interval).
Case 2:
If SMIs happen between (3) and (4) above, then we can end up with a loops_per_jiffy value that is too high. And with current i386 code, too high lpj value (greater than 17M) can result in a overflow in delay.c:__const_udelay() again resulting in shorter delay and panic().
Solution:
The patch below makes the calibration routine aware of asynchronous events like SMIs. We increase the delay calibration time and also identify any significant errors (greater than 12.5%) in the calibration and notify it to user.
Patch below changes both i386 and x86-64 architectures to use this new and improved calibrate_delay_direct() routine.
/arch/i386/kernel/timers/timer.c renamed from /arch/i386/kernel/timers/timer.c.orig +9 -0
@@ -64,3 +64,12 @@ struct timer_opts* __init select_timer(vpanic ("select_timer: Cannot find a suitable timer\n" );return NULL ; } + +int read_current_timer (unsigned long *timer_val) +{ +if (cur_timer->read_timer) { + *timer_val = cur_timer->read_timer (); +return 0 ; + } +return -1 ; +}
/arch/i386/kernel/timers/common.c renamed from /arch/i386/kernel/timers/common.c.orig +9 -0
@@ -139,6 +139,15 @@ bad_calibration: }#endif + +unsigned long read_timer_tsc (void ) +{ +unsigned long retval; +rdtscl (retval); +return retval; +} + +/* calculate cpu_khz */ void init_cpu_khz (void ) {
/arch/i386/kernel/timers/timer_tsc.c renamed from /arch/i386/kernel/timers/timer_tsc.c.orig +1 -0
@@ -572,6 +572,7 @@ static struct timer_opts timer_tsc = { .get_offset = get_offset_tsc, .monotonic_clock = monotonic_clock_tsc, .delay = delay_tsc, + .read_timer = read_timer_tsc, };struct init_timer_opts __initdata timer_tsc_init = {
/arch/i386/kernel/timers/timer_hpet.c renamed from /arch/i386/kernel/timers/timer_hpet.c.orig +1 -0
@@ -183,6 +183,7 @@ static struct timer_opts timer_hpet = { .get_offset = get_offset_hpet, .monotonic_clock = monotonic_clock_hpet, .delay = delay_hpet, + .read_timer = read_timer_tsc, };struct init_timer_opts __initdata timer_hpet_init = {
/arch/i386/kernel/timers/timer_pm.c renamed from /arch/i386/kernel/timers/timer_pm.c.orig +1 -0
@@ -246,6 +246,7 @@ static struct timer_opts timer_pmtmr = { .get_offset = get_offset_pmtmr, .monotonic_clock = monotonic_clock_pmtmr, .delay = delay_pmtmr, + .read_timer = read_timer_tsc, };struct init_timer_opts __initdata timer_pmtmr_init = {
/arch/x86_64/lib/delay.c renamed from /arch/x86_64/lib/delay.c.orig +7 -0
@@ -12,6 +12,7 @@#include <linux/sched.h> #include <linux/delay.h> #include <asm/delay.h> +#include <asm/msr.h> #ifdef CONFIG_SMP #include <asm/smp.h>
@@ -19,6 +20,12 @@int x86_udelay_tsc =0 ;/* Delay via TSC */ +int read_current_timer (unsigned long *timer_value) +{ +rdtscll (*timer_value); +return 0 ; +} +void __delay (unsigned long loops) {unsigned bclock, now;
/include/asm-x86_64/timex.h renamed from /include/asm-x86_64/timex.h.orig +3 -0
@@ -26,6 +26,9 @@ static inline cycles_t get_cycles (void)extern unsigned int cpu_khz; +extern int read_current_timer (unsigned long *timer_value); +#define ARCH_HAS_READ_CURRENT_TIMER 1 +extern struct vxtime_data vxtime;#endif
/include/asm-i386/timer.h renamed from /include/asm-i386/timer.h.orig +2 -0
@@ -22,6 +22,7 @@ struct timer_opts {unsigned long (*get_offset)(void );unsigned long long (*monotonic_clock)(void );void (*delay)(unsigned long ); +unsigned long (*read_timer)(void ); };struct init_timer_opts {
@@ -52,6 +53,7 @@ extern struct init_timer_opts timer_cycl#endif extern unsigned long calibrate_tsc (void ); +extern unsigned long read_timer_tsc (void );extern void init_cpu_khz (void );extern int recalibrate_cpu_khz (void );#ifdef CONFIG_HPET_TIMER
/include/asm-i386/timex.h renamed from /include/asm-i386/timex.h.orig +3 -0
@@ -49,4 +49,7 @@ static inline cycles_t get_cycles (void)extern unsigned long cpu_khz; +extern int read_current_timer (unsigned long *timer_value); +#define ARCH_HAS_READ_CURRENT_TIMER 1 +#endif
/init/calibrate.c renamed from /init/calibrate.c.orig +94 -0
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