Do not enforce unique IO_APIC_ID for Xeon processors in EM64T mode (x86_64)
PATCH 1/1 Do not enforce unique IO_APIC_ID for Xeon processors in EM64T mode (x86_64)
This patch disables unique IO_APIC_ID check for xAPIC systems running in EM64T mode. Xeon-based ES7000s panic failing this unnecessary check. I added IOAPIC_ID_CHECK config option and turned it off for Intel processors. Also added the boot option that overrides default and turnes this check on/off in case it is needed for some reason. Hope this is acceptable way to fix the problem.
Signed-off by: Natalie Protasevich <[email protected]>
---
arch/x86_64/kernel/setup.c renamed from arch/x86_64/kernel/setup.c~no-ioapic-check-x86_64 +6 -0
@@ -346,6 +346,9 @@ static __init void parse_cmdline_early ( ioapic_force =1 ; } +if (!memcmp (from,"ioapic_id_check=" ,16 )) +ioapic_id_check_setup (from+16 ); +if (!memcmp (from,"mem=" ,4 ))parse_memopt (from+4 , &from);
@@ -547,6 +550,9 @@ void __init setup_arch(char **cmdline_p) data_resource.start =virt_to_phys (&_etext); data_resource.end =virt_to_phys (&_edata)-1 ; +#ifdef CONFIG_NO_IOAPIC_CHECK + skip_ioapic_id_check =1 ; +#endif parse_cmdline_early (cmdline_p);early_identify_cpu (&boot_cpu_data);
arch/x86_64/kernel/io_apic.c renamed from arch/x86_64/kernel/io_apic.c~no-ioapic-check-x86_64 +18 -3
@@ -216,6 +216,7 @@ static void clear_IO_APIC (void)static int pirq_entries [MAX_PIRQS ];static int pirqs_enabled;int skip_ioapic_setup; +int skip_ioapic_id_check;int ioapic_force;/* dummy parsing: see setup.c */
@@ -233,8 +234,19 @@ static int __init enable_ioapic_setup(chreturn 1 ; } +int __init ioapic_id_check_setup (char *str) +{ +if (!strncmp (str,"on" ,2 )) { + skip_ioapic_id_check =0 ; + }else if (!strncmp (str,"off" ,3 )) { + skip_ioapic_id_check =1 ; + } +return 1 ; +} +__setup ("noapic" , disable_ioapic_setup);__setup ("apic" , enable_ioapic_setup); +__setup ("ioapic_id_check=" , ioapic_id_check_setup);#include <asm/pci-direct.h> #include <linux/pci_ids.h>
@@ -1867,12 +1879,15 @@ int __init io_apic_get_unique_id (int ioint i =0 ;/* +* P4-class systems take advantage of APIC system bus architecture. +*/ + +if (skip_ioapic_id_check) +return apic_id; +/* * The P4 platform supports up to 256 APIC IDs on two separate APIC * buses (one for LAPICs, one for IOAPICs), where predecessors only * supports up to 16 on one shared APIC bus. -* -* TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full -* advantage of new APIC bus architecture. */ if (physids_empty (apic_id_map))
arch/x86_64/Kconfig renamed from arch/x86_64/Kconfig~no-ioapic-check-x86_64 +5 -0
@@ -163,6 +163,11 @@ config X86_IO_APIC bool default y +config NO_IOAPIC_CHECK + bool + depends on GENERIC_CPU || MPSC + default y + config X86_LOCAL_APIC bool default y
include/asm-x86_64/io_apic.h renamed from include/asm-x86_64/io_apic.h~no-ioapic-check-x86_64 +3 -0
@@ -195,6 +195,9 @@ static inline void io_apic_sync(unsigned/* 1 if "noapic" boot option passed */ extern int skip_ioapic_setup; +/* 1 if "ioapic_id_check=off" boot option passed */ +extern int skip_ioapic_id_check; +/* * If we use the IO-APIC for IRQ routing, disable automatic * assignment of PCI IRQ's.
include/asm-x86_64/proto.h renamed from include/asm-x86_64/proto.h~no-ioapic-check-x86_64 +2 -0
@@ -75,6 +75,7 @@ extern void syscall32_cpu_init(void);extern void setup_node_bootmem (int nodeid,unsigned long start,unsigned long end);extern void check_ioapic (void ); +extern int ioapic_id_check_setup (char *str);extern void check_efer (void );extern int unhandled_signal (struct task_struct *tsk,int sig);
@@ -93,6 +94,7 @@ extern int disable_apic;extern unsigned cpu_khz;extern int ioapic_force;extern int skip_ioapic_setup; +extern int extern int skip_ioapic_id_check;extern int acpi_ht;extern int acpi_disabled;
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Quoted 11 lines · On Thu, 2005-05-05 at 18:11, [email protected] wrote:
This patch disables unique
IO_APIC_IDcheck for xAPIC systems running in EM64T mode. Xeon-based ES7000s panic failing this unnecessary check. I addedIOAPIC_ID_CHECKconfig option and turned it off for Intel processors. Also added the boot option that overrides default and turnes this check on/off in case it is needed for some reason. Hope this is acceptable way to fix the problem.Signed-off by: Natalie Protasevich <[email protected]>
arch/x86_64/Kconfig config X86_IO_APIC · line 170
Quoted 5 lines
arch/x86_64/Kconfig renamed from arch/x86_64/Kconfig~no-ioapic-check-x86_64 +5
-0+config NO_IOAPIC_CHECK + bool + depends on GENERIC_CPU || MPSC + default y +
A run-time solution would be preferable to adding a config option that only changes the default behaviour.
In general, the more config options, the more kernels we force distros to build and support. We really want to going the other way and simplifying, when possible.
cheers,
-Len
Quoted 8 lines · On Thu, 5 May 2005 [email protected] wrote:
This patch disables unique
IO_APIC_IDcheck for xAPIC systems running in EM64T mode. Xeon-based ES7000s panic failing this unnecessary check. I addedIOAPIC_ID_CHECKconfig option and turned it off for Intel processors. Also added the boot option that overrides default and turnes this check on/off in case it is needed for some reason. Hope this is acceptable way to fix the problem.
Perhaps just make it unconditional on xAPIC, i also can't see when you'd need the kernel parameter, so perhaps lets just leave that out.
Thanks,
Zwane
Quoted 3 lines · On Thu, May 05, 2005 at 03:11:16PM -0700, [email protected] wrote:
This patch disables unique
IO_APIC_IDcheck for xAPIC systems running in EM64T mode. Xeon-based ES7000s panic failing this unnecessary check. I addedIOAPIC_ID_CHECKconfig option and turned it off for Intel processors. Also added the boot option that overrides default and turnes this check on/off in case it is needed for some reason. Hope this is acceptable way to fix the problem.
I think we can turn it off for all x86-64 systems. Near all EM64T systems have xAPIC. AMD processors don't need it neither. That would only leave the new IBM summit2 chipset, but I suppose they also don't need this (James please complain if I am wrong)
So can you please do a new patch that just removes this code?
More tricky will be to do the equivalent patch on i386 because they still need to support the pre XAPICs and have to detect this case. I suppose an heuristic like
if (cpu is P6 or earlier and from Intel)
enable
else
disable
would be good enough.
Thanks
-Andi