qla2xxx: Add ISP24xx support.

@@ -62,6 +62,22 @@
 #define PCI_DEVICE_ID_QLOGIC_ISP6322	0x6322
 #endif
 
+#ifndef PCI_DEVICE_ID_QLOGIC_ISP2422
+#define PCI_DEVICE_ID_QLOGIC_ISP2422	0x2422
+#endif
+
+#ifndef PCI_DEVICE_ID_QLOGIC_ISP2432
+#define PCI_DEVICE_ID_QLOGIC_ISP2432	0x2432
+#endif
+
+#ifndef PCI_DEVICE_ID_QLOGIC_ISP2512
+#define PCI_DEVICE_ID_QLOGIC_ISP2512	0x2512
+#endif
+
+#ifndef PCI_DEVICE_ID_QLOGIC_ISP2522
+#define PCI_DEVICE_ID_QLOGIC_ISP2522	0x2522
+#endif
+
 #if defined(CONFIG_SCSI_QLA21XX) || defined(CONFIG_SCSI_QLA21XX_MODULE)
 #define IS_QLA2100(ha)	((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2100)
 #else

@@ -96,9 +112,28 @@
 #define IS_QLA6322(ha)	0
 #endif
 
+#if defined(CONFIG_SCSI_QLA24XX) || defined(CONFIG_SCSI_QLA24XX_MODULE)
+#define IS_QLA2422(ha)	((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422)
+#define IS_QLA2432(ha)	((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432)
+#else
+#define IS_QLA2422(ha)	0
+#define IS_QLA2432(ha)	0
+#endif
+
+#if defined(CONFIG_SCSI_QLA25XX) || defined(CONFIG_SCSI_QLA25XX_MODULE)
+#define IS_QLA2512(ha)	((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2512)
+#define IS_QLA2522(ha)	((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2522)
+#else
+#define IS_QLA2512(ha)	0
+#define IS_QLA2522(ha)	0
+#endif
+
 #define IS_QLA23XX(ha)	(IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
     			 IS_QLA6312(ha) || IS_QLA6322(ha))
 
+#define IS_QLA24XX(ha)	(IS_QLA2422(ha) || IS_QLA2432(ha))
+#define IS_QLA25XX(ha)	(IS_QLA2512(ha) || IS_QLA2522(ha))
+
 /*
  * Only non-ISP2[12]00 have extended addressing support in the firmware.
  */

@@ -212,10 +247,18 @@
 #define MANAGEMENT_SERVER	0xfe
 #define BROADCAST		0xff
 
-#define RESERVED_LOOP_ID(x)	((x > LAST_LOCAL_LOOP_ID && \
-				 x < SNS_FIRST_LOOP_ID) || \
-				 x == MANAGEMENT_SERVER || \
-				 x == BROADCAST)
+/*
+ * There is no correspondence between an N-PORT id and an AL_PA.  Therefore the
+ * valid range of an N-PORT id is 0 through 0x7ef.
+ */
+#define NPH_LAST_HANDLE		0x7ef
+#define NPH_SNS			0x7fc		/*  FFFFFC */
+#define NPH_FABRIC_CONTROLLER	0x7fd		/*  FFFFFD */
+#define NPH_F_PORT		0x7fe		/*  FFFFFE */
+#define NPH_IP_BROADCAST	0x7ff		/*  FFFFFF */
+
+#define MAX_CMDSZ	16		/* SCSI maximum CDB size. */
+#include "qla_fw.h"
 
 /*
  * Timeout timer counts in seconds

@@ -232,6 +275,7 @@
 #define REQUEST_ENTRY_CNT_2100		128	/* Number of request entries. */
 #define REQUEST_ENTRY_CNT_2200		2048	/* Number of request entries. */
 #define REQUEST_ENTRY_CNT_2XXX_EXT_MEM	4096	/* Number of request entries. */
+#define REQUEST_ENTRY_CNT_24XX		4096	/* Number of request entries. */
 #define RESPONSE_ENTRY_CNT_2100		64	/* Number of response entries.*/
 #define RESPONSE_ENTRY_CNT_2300		512	/* Number of response entries.*/
 

@@ -525,6 +569,8 @@ typedef struct {
 #define MBS_LOOP_ID_USED		0x4008
 #define MBS_ALL_IDS_IN_USE		0x4009
 #define MBS_NOT_LOGGED_IN		0x400A
+#define MBS_LINK_DOWN_ERROR		0x400B
+#define MBS_DIAG_ECHO_TEST_ERROR	0x400C
 
 /*
  * ISP mailbox asynchronous event status codes

@@ -576,7 +622,7 @@ typedef struct {
 #define FO1_CTIO_RETRY			BIT_3
 #define FO1_DISABLE_LIP_F7_SW		BIT_4
 #define FO1_DISABLE_100MS_LOS_WAIT	BIT_5
-#define FO1_DISABLE_GPIO6_7		BIT_6
+#define FO1_DISABLE_GPIO6_7		BIT_6	/* LED bits */
 #define FO1_AE_ON_LOOP_INIT_ERR		BIT_7
 #define FO1_SET_EMPHASIS_SWING		BIT_8
 #define FO1_AE_AUTO_BYPASS		BIT_9

@@ -591,6 +637,15 @@ typedef struct {
 #define FO3_ENABLE_EMERG_IOCB		BIT_0
 #define FO3_AE_RND_ERROR		BIT_1
 
+/* 24XX additional firmware options */
+#define ADD_FO_COUNT			3
+#define ADD_FO1_DISABLE_GPIO_LED_CTRL	BIT_6	/* LED bits */
+#define ADD_FO1_ENABLE_PUREX_IOCB	BIT_10
+
+#define ADD_FO2_ENABLE_SEL_CLS2		BIT_5
+
+#define ADD_FO3_NO_ABT_ON_LINK_DOWN	BIT_14
+
 /*
  * ISP mailbox commands
  */

@@ -659,6 +714,22 @@ typedef struct {
 #define MBC_SEND_LFA_COMMAND		0x7D	/* Send Loop Fabric Address */
 #define MBC_LUN_RESET			0x7E	/* Send LUN reset */
 
+/*
+ * ISP24xx mailbox commands
+ */
+#define MBC_SERDES_PARAMS		0x10	/* Serdes Tx Parameters. */
+#define MBC_GET_IOCB_STATUS		0x12	/* Get IOCB status command. */
+#define MBC_GET_TIMEOUT_PARAMS		0x22	/* Get FW timeouts. */
+#define MBC_GEN_SYSTEM_ERROR		0x2a	/* Generate System Error. */
+#define MBC_SET_TIMEOUT_PARAMS		0x32	/* Set FW timeouts. */
+#define MBC_MID_INITIALIZE_FIRMWARE	0x48	/* MID Initialize firmware. */
+#define MBC_MID_GET_VP_DATABASE		0x49	/* MID Get VP Database. */
+#define MBC_MID_GET_VP_ENTRY		0x4a	/* MID Get VP Entry. */
+#define MBC_HOST_MEMORY_COPY		0x53	/* Host Memory Copy. */
+#define MBC_SEND_RNFT_ELS		0x5e	/* Send RNFT ELS request */
+#define MBC_GET_LINK_PRIV_STATS		0x6d	/* Get link & private data. */
+#define MBC_SET_VENDOR_ID		0x76	/* Set Vendor ID. */
+
 /* Firmware return data sizes */
 #define FCAL_MAP_SIZE	128
 

@@ -888,6 +959,9 @@ typedef struct {
 /*
  * Get Link Status mailbox command return buffer.
  */
+#define GLSO_SEND_RPS	BIT_0
+#define GLSO_USE_DID	BIT_3
+
 typedef struct {
 	uint32_t	link_fail_cnt;
 	uint32_t	loss_sync_cnt;

@@ -1182,7 +1256,6 @@ do {							\
  * ISP queue - command entry structure definition.
  */
 #define COMMAND_TYPE	0x11		/* Command entry */
-#define MAX_CMDSZ	16		/* SCSI maximum CDB size. */
 typedef struct {
 	uint8_t entry_type;		/* Entry type. */
 	uint8_t entry_count;		/* Entry count. */

@@ -1305,11 +1378,16 @@ typedef struct {
 /*
  * Status entry entry status
  */
+#define RF_RQ_DMA_ERROR	BIT_6		/* Request Queue DMA error. */
 #define RF_INV_E_ORDER	BIT_5		/* Invalid entry order. */
 #define RF_INV_E_COUNT	BIT_4		/* Invalid entry count. */
 #define RF_INV_E_PARAM	BIT_3		/* Invalid entry parameter. */
 #define RF_INV_E_TYPE	BIT_2		/* Invalid entry type. */
 #define RF_BUSY		BIT_1		/* Busy */
+#define RF_MASK		(RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
+			 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
+#define RF_MASK_24XX	(RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
+			 RF_INV_E_TYPE)
 
 /*
  * Status entry SCSI status bit definitions.

@@ -1524,9 +1602,6 @@ typedef struct {
 	port_id_t d_id;
 	uint8_t node_name[WWN_SIZE];
 	uint8_t port_name[WWN_SIZE];
-	uint32_t type;
-#define SW_TYPE_IP	BIT_1
-#define SW_TYPE_SCSI	BIT_0
 } sw_info_t;
 
 /*

@@ -1541,6 +1616,8 @@ typedef struct {
 	union {
 		cmd_a64_entry_t cmd;
 		sts_entry_t rsp;
+		struct cmd_type_7 cmd24;
+		struct sts_entry_24xx rsp24;
 	} p;
 	uint8_t inq[INQ_DATA_SIZE];
 } inq_cmd_rsp_t;

@@ -1576,10 +1653,13 @@ typedef struct {
 	union {
 		cmd_a64_entry_t cmd;
 		sts_entry_t rsp;
+		struct cmd_type_7 cmd24;
+		struct sts_entry_24xx rsp24;
 	} p;
 	rpt_lun_lst_t list;
 } rpt_lun_cmd_rsp_t;
 
+
 /*
  * Fibre channel port type.
  */

@@ -1669,6 +1749,7 @@ typedef struct fc_port {
 #define FCF_FAILOVER_DISABLE	BIT_22
 #define FCF_DSXXX_DEVICE	BIT_23
 #define FCF_AA_EVA_DEVICE	BIT_24
+#define FCF_AA_MSA_DEVICE	BIT_25
 
 /* No loop ID flag. */
 #define FC_NO_LOOP_ID		0x1000

@@ -1940,6 +2021,7 @@ struct qla_board_info {
 
 	char isp_name[8];
 	struct qla_fw_info *fw_info;
+	char *fw_fname;;
 };
 
 /* Return data from MBC_GET_ID_LIST call. */

@@ -1949,6 +2031,7 @@ struct gid_list_info {
 	uint8_t	domain;		
 	uint8_t	loop_id_2100;	/* ISP2100/ISP2200 -- 4 bytes. */
 	uint16_t loop_id;	/* ISP23XX         -- 6 bytes. */
+	uint16_t reserved_1;	/* ISP24XX         -- 8 bytes. */
 };
 #define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
 

@@ -1982,6 +2065,8 @@ typedef struct scsi_qla_host {
 		uint32_t	enable_lip_full_login	:1;
 		uint32_t	enable_target_reset	:1;
 		uint32_t	enable_led_scheme	:1;
+		uint32_t	msi_enabled		:1;
+		uint32_t	msix_enabled		:1;
 	} flags;
 
 	atomic_t	loop_state;

@@ -2018,6 +2103,7 @@ typedef struct scsi_qla_host {
 #define IODESC_PROCESS_NEEDED	22      /* IO descriptor processing needed */
 #define IOCTL_ERROR_RECOVERY	23      
 #define LOOP_RESET_NEEDED	24
+#define BEACON_BLINK_NEEDED	25
 
 	uint32_t	device_flags;
 #define DFLG_LOCAL_DEVICES		BIT_0

@@ -2058,6 +2144,7 @@ typedef struct scsi_qla_host {
 	uint16_t        rsp_ring_index;     /* Current index. */
 	uint16_t	response_q_length;
     
+	int		(*start_scsi)(srb_t *);
 	uint16_t	(*calc_request_entries)(uint16_t);
 	void		(*build_scsi_iocbs)(srb_t *, cmd_entry_t *, uint16_t);
 

@@ -2102,6 +2189,7 @@ typedef struct scsi_qla_host {
 	uint8_t		serial2;
 
 	/* NVRAM configuration data */
+	uint16_t	nvram_size;
 	uint16_t	nvram_base;
 
 	uint16_t	loop_reset_delay;

@@ -2161,7 +2249,8 @@ typedef struct scsi_qla_host {
 	struct dma_pool *s_dma_pool;
 
 	dma_addr_t	init_cb_dma;
-	init_cb_t       *init_cb;
+	init_cb_t	*init_cb;
+	int		init_cb_size;
 
 	dma_addr_t	iodesc_pd_dma;
 	port_database_t *iodesc_pd;

@@ -2202,6 +2291,7 @@ typedef struct scsi_qla_host {
 
 	uint16_t	fw_options[16];		/* slots: 1,2,3,10,11 */
 	uint8_t		fw_seriallink_options[4];
+	uint16_t	fw_seriallink_options24[4];
 
 	/* Firmware dump information. */
 	void		*fw_dump;

@@ -2210,8 +2300,13 @@ typedef struct scsi_qla_host {
 	char		*fw_dump_buffer;
 	int		fw_dump_buffer_len;
 
+//ISP24xx
+	int		fw_dumped;
+	void		*fw_dump24;
+	int		fw_dump24_len;
+
 	uint8_t		host_str[16];
-	uint16_t	pci_attr;
+	uint32_t	pci_attr;
 
 	uint16_t	product_id[4];
 

@@ -2219,8 +2314,8 @@ typedef struct scsi_qla_host {
 #define BINZERO		"\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
 	char		*model_desc;
 
-	uint8_t     node_name[WWN_SIZE];
-	uint8_t     nvram_version; 
+	uint8_t		*node_name;
+	uint8_t		*port_name;
 	uint32_t    isp_abort_cnt;
 
 	/* Needed for BEACON */

1,076 lines not on this page · raw message

@@ -1368,8 +1368,6 @@ qla2x00_nvram_config(scsi_qla_host_t *ha
 	/*
 	 * Set host adapter parameters.
 	 */
-	ha->nvram_version = nv->nvram_version;
-
 	ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
 	/* Always load RISC code on non ISP2[12]00 chips. */
 	if (!IS_QLA2100(ha) && !IS_QLA2200(ha))

@@ -2141,7 +2139,7 @@ qla2x00_find_all_fabric_devs(scsi_qla_ho
 	loop_id = ha->min_external_loopid;
 
 	for (; loop_id <= ha->last_loop_id; loop_id++) {
-		if (RESERVED_LOOP_ID(loop_id))
+		if (qla2x00_is_reserved_id(ha, loop_id))
 			continue;
 
 		if (atomic_read(&ha->loop_down_timer) ||

@@ -2311,7 +2309,7 @@ qla2x00_find_new_loop_id(scsi_qla_host_t
 		}
 
 		/* Skip reserved loop IDs. */
-		while (RESERVED_LOOP_ID(dev->loop_id)) {
+		while (qla2x00_is_reserved_id(ha, dev->loop_id)) {
 			dev->loop_id++;
 		}
 

@@ -273,3 +273,14 @@ qla2x00_delete_timer_from_cmd(srb_t *sp)
 	}
 }
 
+
+static inline int qla2x00_is_reserved_id(scsi_qla_host_t *, uint16_t);
+static inline int
+qla2x00_is_reserved_id(scsi_qla_host_t *ha, uint16_t loop_id)
+{
+	if (IS_QLA24XX(ha) || IS_QLA25XX(ha))
+		return (loop_id > NPH_LAST_HANDLE);
+
+	return ((loop_id > ha->last_loop_id && loop_id < SNS_FIRST_LOOP_ID) ||
+	    loop_id == MANAGEMENT_SERVER || loop_id == BROADCAST);
+};

@@ -975,6 +975,1185 @@ qla_uprintf(char **uiter, char *fmt, ...
 	return (len);
 }
 
+
+void
+qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
+{
+	int		rval;
+	uint32_t	cnt, timer;
+	uint32_t	risc_address;
+	uint16_t	mb[4];
+
+	uint32_t	stat;
+	struct device_reg_24xx __iomem *reg;
+	uint32_t __iomem *dmp_reg;
+	uint32_t	*iter_reg;
+	uint16_t __iomem *mbx_reg;
+	unsigned long	flags;
+	struct qla24xx_fw_dump *fw;
+	uint32_t	ext_mem_cnt;
+
+	reg = (struct device_reg_24xx __iomem *)ha->iobase;
+	risc_address = ext_mem_cnt = 0;
+	memset(mb, 0, sizeof(mb));
+	flags = 0;
+
+	if (!hardware_locked)
+		spin_lock_irqsave(&ha->hardware_lock, flags);
+
+	if (!ha->fw_dump24) {
+		qla_printk(KERN_WARNING, ha,
+		    "No buffer available for dump!!!\n");
+		goto qla24xx_fw_dump_failed;
+	}
+
+	if (ha->fw_dumped) {
+		qla_printk(KERN_WARNING, ha,
+		    "Firmware has been previously dumped (%p) -- ignoring "
+		    "request...\n", ha->fw_dump24);
+		goto qla24xx_fw_dump_failed;
+	}
+	fw = (struct qla24xx_fw_dump *) ha->fw_dump24;
+
+	rval = QLA_SUCCESS;
+	fw->hccr = RD_REG_DWORD(&reg->hccr);
+
+	/* Pause RISC. */
+	if ((fw->hccr & HCCRX_RISC_PAUSE) == 0) {
+		WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET |
+		    HCCRX_CLR_HOST_INT);
+		RD_REG_DWORD(&reg->hccr);		/* PCI Posting. */
+		WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
+		for (cnt = 30000;
+		    (RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0 &&
+		    rval == QLA_SUCCESS; cnt--) {
+			if (cnt)
+				udelay(100);
+			else
+				rval = QLA_FUNCTION_TIMEOUT;
+		}
+	}
+
+	/* Disable interrupts. */
+	WRT_REG_DWORD(&reg->ictrl, 0);
+	RD_REG_DWORD(&reg->ictrl);
+
+	if (rval == QLA_SUCCESS) {
+		/* Host interface registers. */
+		dmp_reg = (uint32_t __iomem *)(reg + 0);
+		for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
+			fw->host_reg[cnt] = RD_REG_DWORD(dmp_reg++);
+
+		/* Mailbox registers. */
+		mbx_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
+		for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
+			fw->mailbox_reg[cnt] = RD_REG_WORD(mbx_reg++);
+
+		/* Transfer sequence registers. */
+		iter_reg = fw->xseq_gp_reg;
+		WRT_REG_DWORD(&reg->iobase_addr, 0xBF00);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0xBF10);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0xBF20);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0xBF30);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0xBF40);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0xBF50);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0xBF60);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0xBF70);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0xBFE0);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++)
+			fw->xseq_0_reg[cnt] = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0xBFF0);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++)
+			fw->xseq_1_reg[cnt] = RD_REG_DWORD(dmp_reg++);
+
+		/* Receive sequence registers. */
+		iter_reg = fw->rseq_gp_reg;
+		WRT_REG_DWORD(&reg->iobase_addr, 0xFF00);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0xFF10);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0xFF20);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0xFF30);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0xFF40);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0xFF50);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0xFF60);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0xFF70);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0xFFD0);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++)
+			fw->rseq_0_reg[cnt] = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0xFFE0);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++)
+			fw->rseq_1_reg[cnt] = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0xFFF0);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++)
+			fw->rseq_2_reg[cnt] = RD_REG_DWORD(dmp_reg++);
+
+		/* Command DMA registers. */
+		WRT_REG_DWORD(&reg->iobase_addr, 0x7100);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++)
+			fw->cmd_dma_reg[cnt] = RD_REG_DWORD(dmp_reg++);
+
+		/* Queues. */
+		iter_reg = fw->req0_dma_reg;
+		WRT_REG_DWORD(&reg->iobase_addr, 0x7200);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 8; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
+		for (cnt = 0; cnt < 7; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		iter_reg = fw->resp0_dma_reg;
+		WRT_REG_DWORD(&reg->iobase_addr, 0x7300);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 8; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
+		for (cnt = 0; cnt < 7; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		iter_reg = fw->req1_dma_reg;
+		WRT_REG_DWORD(&reg->iobase_addr, 0x7400);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 8; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
+		for (cnt = 0; cnt < 7; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		/* Transmit DMA registers. */
+		iter_reg = fw->xmt0_dma_reg;
+		WRT_REG_DWORD(&reg->iobase_addr, 0x7600);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x7610);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		iter_reg = fw->xmt1_dma_reg;
+		WRT_REG_DWORD(&reg->iobase_addr, 0x7620);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x7630);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		iter_reg = fw->xmt2_dma_reg;
+		WRT_REG_DWORD(&reg->iobase_addr, 0x7640);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x7650);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		iter_reg = fw->xmt3_dma_reg;
+		WRT_REG_DWORD(&reg->iobase_addr, 0x7660);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x7670);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		iter_reg = fw->xmt4_dma_reg;
+		WRT_REG_DWORD(&reg->iobase_addr, 0x7680);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x7690);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x76A0);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++)
+			fw->xmt_data_dma_reg[cnt] = RD_REG_DWORD(dmp_reg++);
+
+		/* Receive DMA registers. */
+		iter_reg = fw->rcvt0_data_dma_reg;
+		WRT_REG_DWORD(&reg->iobase_addr, 0x7700);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x7710);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		iter_reg = fw->rcvt1_data_dma_reg;
+		WRT_REG_DWORD(&reg->iobase_addr, 0x7720);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x7730);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		/* RISC registers. */
+		iter_reg = fw->risc_gp_reg;
+		WRT_REG_DWORD(&reg->iobase_addr, 0x0F00);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x0F10);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x0F20);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x0F30);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x0F40);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x0F50);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x0F60);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
+		RD_REG_DWORD(&reg->iobase_addr);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
+		WRT_REG_DWORD(dmp_reg, 0xB0000000);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
+		fw->shadow_reg[0] = RD_REG_DWORD(dmp_reg);
+
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
+		WRT_REG_DWORD(dmp_reg, 0xB0100000);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
+		fw->shadow_reg[1] = RD_REG_DWORD(dmp_reg);
+
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
+		WRT_REG_DWORD(dmp_reg, 0xB0200000);
+		dmp_reg = (uint32_t *)((uint8_t *)reg + 0xFC);
+		fw->shadow_reg[2] = RD_REG_DWORD(dmp_reg);
+
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
+		WRT_REG_DWORD(dmp_reg, 0xB0300000);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
+		fw->shadow_reg[3] = RD_REG_DWORD(dmp_reg);
+
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
+		WRT_REG_DWORD(dmp_reg, 0xB0400000);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
+		fw->shadow_reg[4] = RD_REG_DWORD(dmp_reg);
+
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
+		WRT_REG_DWORD(dmp_reg, 0xB0500000);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
+		fw->shadow_reg[5] = RD_REG_DWORD(dmp_reg);
+
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
+		WRT_REG_DWORD(dmp_reg, 0xB0600000);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
+		fw->shadow_reg[6] = RD_REG_DWORD(dmp_reg);
+
+		/* Local memory controller registers. */
+		iter_reg = fw->lmc_reg;
+		WRT_REG_DWORD(&reg->iobase_addr, 0x3000);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x3010);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x3020);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x3030);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x3040);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x3050);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x3060);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		/* Fibre Protocol Module registers. */
+		iter_reg = fw->fpm_hdw_reg;
+		WRT_REG_DWORD(&reg->iobase_addr, 0x4000);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x4010);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x4020);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x4030);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x4040);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x4050);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x4060);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x4070);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x4080);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x4090);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x40A0);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x40B0);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		/* Frame Buffer registers. */
+		iter_reg = fw->fb_hdw_reg;
+		WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x6020);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x6030);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x6040);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x6100);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x6130);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x6150);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x6170);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x6190);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		WRT_REG_DWORD(&reg->iobase_addr, 0x61B0);
+		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
+		for (cnt = 0; cnt < 16; cnt++)
+			*iter_reg++ = RD_REG_DWORD(dmp_reg++);
+
+		/* Reset RISC. */
+		WRT_REG_DWORD(&reg->ctrl_status,
+		    CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
+		for (cnt = 0; cnt < 30000; cnt++) {
+			if ((RD_REG_DWORD(&reg->ctrl_status) &
+			    CSRX_DMA_ACTIVE) == 0)
+				break;
+
+			udelay(10);
+		}
+
+		WRT_REG_DWORD(&reg->ctrl_status,
+		    CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
+		udelay(20);
+		for (cnt = 0; cnt < 30000; cnt++) {
+			if ((RD_REG_DWORD(&reg->ctrl_status) &
+			    CSRX_ISP_SOFT_RESET) == 0)
+				break;
+
+			udelay(10);
+		}
+		WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
+		RD_REG_DWORD(&reg->hccr);             /* PCI Posting. */
+	}
+
+	for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
+	    rval == QLA_SUCCESS; cnt--) {
+		if (cnt)
+			udelay(100);
+		else
+			rval = QLA_FUNCTION_TIMEOUT;
+	}
+
+	/* Memory. */
+	if (rval == QLA_SUCCESS) {
+		/* Code RAM. */
+		risc_address = 0x20000;
+		WRT_REG_WORD(&reg->mailbox0, MBC_READ_RAM_EXTENDED);
+		clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
+	}
+	for (cnt = 0; cnt < sizeof(fw->code_ram) / 4 && rval == QLA_SUCCESS;
+	    cnt++, risc_address++) {
+		WRT_REG_WORD(&reg->mailbox1, LSW(risc_address));
+		WRT_REG_WORD(&reg->mailbox8, MSW(risc_address));
+		RD_REG_WORD(&reg->mailbox8);
+		WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
+
+		for (timer = 6000000; timer; timer--) {
+			/* Check for pending interrupts. */
+			stat = RD_REG_DWORD(&reg->host_status);
+			if (stat & HSRX_RISC_INT) {
+				stat &= 0xff;
+
+				if (stat == 0x1 || stat == 0x2 ||
+				    stat == 0x10 || stat == 0x11) {
+					set_bit(MBX_INTERRUPT,
+					    &ha->mbx_cmd_flags);
+
+					mb[0] = RD_REG_WORD(&reg->mailbox0);
+					mb[2] = RD_REG_WORD(&reg->mailbox2);
+					mb[3] = RD_REG_WORD(&reg->mailbox3);
+
+					WRT_REG_DWORD(&reg->hccr,
+					    HCCRX_CLR_RISC_INT);
+					RD_REG_DWORD(&reg->hccr);
+					break;
+				}
+
+				/* Clear this intr; it wasn't a mailbox intr */
+				WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
+				RD_REG_DWORD(&reg->hccr);
+			}
+			udelay(5);
+		}
+
+		if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
+			rval = mb[0] & MBS_MASK;
+			fw->code_ram[cnt] = (mb[3] << 16) | mb[2];
+		} else {
+			rval = QLA_FUNCTION_FAILED;
+		}
+	}
+
+	if (rval == QLA_SUCCESS) {
+		/* External Memory. */
+		risc_address = 0x100000;
+		ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1;
+		WRT_REG_WORD(&reg->mailbox0, MBC_READ_RAM_EXTENDED);
+		clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
+	}
+	for (cnt = 0; cnt < ext_mem_cnt && rval == QLA_SUCCESS;
+	    cnt++, risc_address++) {
+		WRT_REG_WORD(&reg->mailbox1, LSW(risc_address));
+		WRT_REG_WORD(&reg->mailbox8, MSW(risc_address));
+		RD_REG_WORD(&reg->mailbox8);
+		WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
+
+		for (timer = 6000000; timer; timer--) {
+			/* Check for pending interrupts. */
+			stat = RD_REG_DWORD(&reg->host_status);
+			if (stat & HSRX_RISC_INT) {
+				stat &= 0xff;
+
+				if (stat == 0x1 || stat == 0x2 ||
+				    stat == 0x10 || stat == 0x11) {
+					set_bit(MBX_INTERRUPT,
+					    &ha->mbx_cmd_flags);
+
+					mb[0] = RD_REG_WORD(&reg->mailbox0);
+					mb[2] = RD_REG_WORD(&reg->mailbox2);
+					mb[3] = RD_REG_WORD(&reg->mailbox3);
+
+					WRT_REG_DWORD(&reg->hccr,
+					    HCCRX_CLR_RISC_INT);
+					RD_REG_DWORD(&reg->hccr);
+					break;
+				}
+
+				/* Clear this intr; it wasn't a mailbox intr */
+				WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
+				RD_REG_DWORD(&reg->hccr);
+			}
+			udelay(5);
+		}
+
+		if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
+			rval = mb[0] & MBS_MASK;
+			fw->ext_mem[cnt] = (mb[3] << 16) | mb[2];
+		} else {
+			rval = QLA_FUNCTION_FAILED;
+		}
+	}
+
+	if (rval != QLA_SUCCESS) {
+		qla_printk(KERN_WARNING, ha,
+		    "Failed to dump firmware (%x)!!!\n", rval);
+		ha->fw_dumped = 0;
+
+	} else {
+		qla_printk(KERN_INFO, ha,
+		    "Firmware dump saved to temp buffer (%ld/%p).\n",
+		    ha->host_no, ha->fw_dump24);
+		ha->fw_dumped = 1;
+	}
+
+qla24xx_fw_dump_failed:
+	if (!hardware_locked)
+		spin_unlock_irqrestore(&ha->hardware_lock, flags);
+}
+
+void
+qla24xx_ascii_fw_dump(scsi_qla_host_t *ha)
+{
+	uint32_t cnt;
+	char *uiter;
+	struct qla24xx_fw_dump *fw;
+	uint32_t ext_mem_cnt;
+
+	uiter = ha->fw_dump_buffer;
+	fw = ha->fw_dump24;
+
+	qla_uprintf(&uiter, "ISP FW Version %d.%02d.%02d Attributes %04x\n",
+	    ha->fw_major_version, ha->fw_minor_version,
+	    ha->fw_subminor_version, ha->fw_attributes);
+
+	qla_uprintf(&uiter, "\nHCCR Register\n%04x\n", fw->hccr);
+
+	qla_uprintf(&uiter, "\nHost Interface Registers");
+	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			qla_uprintf(&uiter, "\n");
+
+		qla_uprintf(&uiter, "%08x ", fw->host_reg[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nMailbox Registers");
+	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) {
+		if (cnt % 8 == 0)
+			qla_uprintf(&uiter, "\n");
+
+		qla_uprintf(&uiter, "%08x ", fw->mailbox_reg[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nXSEQ GP Registers");
+	for (cnt = 0; cnt < sizeof(fw->xseq_gp_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			qla_uprintf(&uiter, "\n");
+
+		qla_uprintf(&uiter, "%08x ", fw->xseq_gp_reg[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nXSEQ-0 Registers");
+	for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			qla_uprintf(&uiter, "\n");
+
+		qla_uprintf(&uiter, "%08x ", fw->xseq_0_reg[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nXSEQ-1 Registers");
+	for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			qla_uprintf(&uiter, "\n");
+
+		qla_uprintf(&uiter, "%08x ", fw->xseq_1_reg[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nRSEQ GP Registers");
+	for (cnt = 0; cnt < sizeof(fw->rseq_gp_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			qla_uprintf(&uiter, "\n");
+
+		qla_uprintf(&uiter, "%08x ", fw->rseq_gp_reg[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nRSEQ-0 Registers");
+	for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			qla_uprintf(&uiter, "\n");
+
+		qla_uprintf(&uiter, "%08x ", fw->rseq_0_reg[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nRSEQ-1 Registers");
+	for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			qla_uprintf(&uiter, "\n");
+
+		qla_uprintf(&uiter, "%08x ", fw->rseq_1_reg[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nRSEQ-2 Registers");
+	for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			qla_uprintf(&uiter, "\n");
+
+		qla_uprintf(&uiter, "%08x ", fw->rseq_2_reg[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nCommand DMA Registers");
+	for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			qla_uprintf(&uiter, "\n");
+
+		qla_uprintf(&uiter, "%08x ", fw->cmd_dma_reg[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nRequest0 Queue DMA Channel Registers");
+	for (cnt = 0; cnt < sizeof(fw->req0_dma_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			qla_uprintf(&uiter, "\n");
+
+		qla_uprintf(&uiter, "%08x ", fw->req0_dma_reg[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nResponse0 Queue DMA Channel Registers");
+	for (cnt = 0; cnt < sizeof(fw->resp0_dma_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			qla_uprintf(&uiter, "\n");
+
+		qla_uprintf(&uiter, "%08x ", fw->resp0_dma_reg[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nRequest1 Queue DMA Channel Registers");
+	for (cnt = 0; cnt < sizeof(fw->req1_dma_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			qla_uprintf(&uiter, "\n");
+
+		qla_uprintf(&uiter, "%08x ", fw->req1_dma_reg[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nXMT0 Data DMA Registers");
+	for (cnt = 0; cnt < sizeof(fw->xmt0_dma_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			qla_uprintf(&uiter, "\n");
+
+		qla_uprintf(&uiter, "%08x ", fw->xmt0_dma_reg[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nXMT1 Data DMA Registers");
+	for (cnt = 0; cnt < sizeof(fw->xmt1_dma_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			qla_uprintf(&uiter, "\n");
+
+		qla_uprintf(&uiter, "%08x ", fw->xmt1_dma_reg[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nXMT2 Data DMA Registers");
+	for (cnt = 0; cnt < sizeof(fw->xmt2_dma_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			qla_uprintf(&uiter, "\n");
+
+		qla_uprintf(&uiter, "%08x ", fw->xmt2_dma_reg[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nXMT3 Data DMA Registers");
+	for (cnt = 0; cnt < sizeof(fw->xmt3_dma_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			qla_uprintf(&uiter, "\n");
+
+		qla_uprintf(&uiter, "%08x ", fw->xmt3_dma_reg[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nXMT4 Data DMA Registers");
+	for (cnt = 0; cnt < sizeof(fw->xmt4_dma_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			qla_uprintf(&uiter, "\n");
+
+		qla_uprintf(&uiter, "%08x ", fw->xmt4_dma_reg[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nXMT Data DMA Common Registers");
+	for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			qla_uprintf(&uiter, "\n");
+
+		qla_uprintf(&uiter, "%08x ", fw->xmt_data_dma_reg[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nRCV Thread 0 Data DMA Registers");
+	for (cnt = 0; cnt < sizeof(fw->rcvt0_data_dma_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			qla_uprintf(&uiter, "\n");
+
+		qla_uprintf(&uiter, "%08x ", fw->rcvt0_data_dma_reg[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nRCV Thread 1 Data DMA Registers");
+	for (cnt = 0; cnt < sizeof(fw->rcvt1_data_dma_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			qla_uprintf(&uiter, "\n");
+
+		qla_uprintf(&uiter, "%08x ", fw->rcvt1_data_dma_reg[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nRISC GP Registers");
+	for (cnt = 0; cnt < sizeof(fw->risc_gp_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			qla_uprintf(&uiter, "\n");
+
+		qla_uprintf(&uiter, "%08x ", fw->risc_gp_reg[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nShadow Registers");
+	for (cnt = 0; cnt < sizeof(fw->shadow_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			qla_uprintf(&uiter, "\n");
+
+		qla_uprintf(&uiter, "%08x ", fw->shadow_reg[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nLMC Registers");
+	for (cnt = 0; cnt < sizeof(fw->lmc_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			qla_uprintf(&uiter, "\n");
+
+		qla_uprintf(&uiter, "%08x ", fw->lmc_reg[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nFPM Hardware Registers");
+	for (cnt = 0; cnt < sizeof(fw->fpm_hdw_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			qla_uprintf(&uiter, "\n");
+
+		qla_uprintf(&uiter, "%08x ", fw->fpm_hdw_reg[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nFB Hardware Registers");
+	for (cnt = 0; cnt < sizeof(fw->fb_hdw_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			qla_uprintf(&uiter, "\n");
+
+		qla_uprintf(&uiter, "%08x ", fw->fb_hdw_reg[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nCode RAM");
+	for (cnt = 0; cnt < sizeof (fw->code_ram) / 4; cnt++) {
+		if (cnt % 8 == 0) {
+			qla_uprintf(&uiter, "\n%08x: ", cnt + 0x20000);
+		}
+		qla_uprintf(&uiter, "%08x ", fw->code_ram[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n\nExternal Memory");
+	ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1;
+	for (cnt = 0; cnt < ext_mem_cnt; cnt++) {
+		if (cnt % 8 == 0) {
+			qla_uprintf(&uiter, "\n%08x: ", cnt + 0x100000);
+		}
+		qla_uprintf(&uiter, "%08x ", fw->ext_mem[cnt]);
+	}
+
+	qla_uprintf(&uiter, "\n[<==END] ISP Debug Dump");
+}
+
+void
+qla24xx_console_fw_dump(scsi_qla_host_t *ha)
+{
+	uint32_t cnt;
+	char *uiter;
+	struct qla24xx_fw_dump *fw;
+	uint32_t ext_mem_cnt;
+
+	uiter = ha->fw_dump_buffer;
+	fw = ha->fw_dump24;
+
+	printk("ISP FW Version %d.%02d.%02d Attributes %04x\n",
+	    ha->fw_major_version, ha->fw_minor_version,
+	    ha->fw_subminor_version, ha->fw_attributes);
+
+	printk("\nHCCR Register\n%04x\n", fw->hccr);
+
+	printk("\nHost Interface Registers");
+	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			printk("\n");
+
+		printk("%08x ", fw->host_reg[cnt]);
+	}
+
+	printk("\n\nMailbox Registers");
+	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) {
+		if (cnt % 8 == 0)
+			printk("\n");
+
+		printk("%08x ", fw->mailbox_reg[cnt]);
+	}
+
+	printk("\n\nXSEQ GP Registers");
+	for (cnt = 0; cnt < sizeof(fw->xseq_gp_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			printk("\n");
+
+		printk("%08x ", fw->xseq_gp_reg[cnt]);
+	}
+
+	printk("\n\nXSEQ-0 Registers");
+	for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			printk("\n");
+
+		printk("%08x ", fw->xseq_0_reg[cnt]);
+	}
+
+	printk("\n\nXSEQ-1 Registers");
+	for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			printk("\n");
+
+		printk("%08x ", fw->xseq_1_reg[cnt]);
+	}
+
+	printk("\n\nRSEQ GP Registers");
+	for (cnt = 0; cnt < sizeof(fw->rseq_gp_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			printk("\n");
+
+		printk("%08x ", fw->rseq_gp_reg[cnt]);
+	}
+
+	printk("\n\nRSEQ-0 Registers");
+	for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			printk("\n");
+
+		printk("%08x ", fw->rseq_0_reg[cnt]);
+	}
+
+	printk("\n\nRSEQ-1 Registers");
+	for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			printk("\n");
+
+		printk("%08x ", fw->rseq_1_reg[cnt]);
+	}
+
+	printk("\n\nRSEQ-2 Registers");
+	for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			printk("\n");
+
+		printk("%08x ", fw->rseq_2_reg[cnt]);
+	}
+
+	printk("\n\nCommand DMA Registers");
+	for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			printk("\n");
+
+		printk("%08x ", fw->cmd_dma_reg[cnt]);
+	}
+
+	printk("\n\nRequest0 Queue DMA Channel Registers");
+	for (cnt = 0; cnt < sizeof(fw->req0_dma_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			printk("\n");
+
+		printk("%08x ", fw->req0_dma_reg[cnt]);
+	}
+
+	printk("\n\nResponse0 Queue DMA Channel Registers");
+	for (cnt = 0; cnt < sizeof(fw->resp0_dma_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			printk("\n");
+
+		printk("%08x ", fw->resp0_dma_reg[cnt]);
+	}
+
+	printk("\n\nRequest1 Queue DMA Channel Registers");
+	for (cnt = 0; cnt < sizeof(fw->req1_dma_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			printk("\n");
+
+		printk("%08x ", fw->req1_dma_reg[cnt]);
+	}
+
+	printk("\n\nXMT0 Data DMA Registers");
+	for (cnt = 0; cnt < sizeof(fw->xmt0_dma_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			printk("\n");
+
+		printk("%08x ", fw->xmt0_dma_reg[cnt]);
+	}
+
+	printk("\n\nXMT1 Data DMA Registers");
+	for (cnt = 0; cnt < sizeof(fw->xmt1_dma_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			printk("\n");
+
+		printk("%08x ", fw->xmt1_dma_reg[cnt]);
+	}
+
+	printk("\n\nXMT2 Data DMA Registers");
+	for (cnt = 0; cnt < sizeof(fw->xmt2_dma_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			printk("\n");
+
+		printk("%08x ", fw->xmt2_dma_reg[cnt]);
+	}
+
+	printk("\n\nXMT3 Data DMA Registers");
+	for (cnt = 0; cnt < sizeof(fw->xmt3_dma_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			printk("\n");
+
+		printk("%08x ", fw->xmt3_dma_reg[cnt]);
+	}
+
+	printk("\n\nXMT4 Data DMA Registers");
+	for (cnt = 0; cnt < sizeof(fw->xmt4_dma_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			printk("\n");
+
+		printk("%08x ", fw->xmt4_dma_reg[cnt]);
+	}
+
+	printk("\n\nXMT Data DMA Common Registers");
+	for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			printk("\n");
+
+		printk("%08x ", fw->xmt_data_dma_reg[cnt]);
+	}
+
+	printk("\n\nRCV Thread 0 Data DMA Registers");
+	for (cnt = 0; cnt < sizeof(fw->rcvt0_data_dma_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			printk("\n");
+
+		printk("%08x ", fw->rcvt0_data_dma_reg[cnt]);
+	}
+
+	printk("\n\nRCV Thread 1 Data DMA Registers");
+	for (cnt = 0; cnt < sizeof(fw->rcvt1_data_dma_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			printk("\n");
+
+		printk("%08x ", fw->rcvt1_data_dma_reg[cnt]);
+	}
+
+	printk("\n\nRISC GP Registers");
+	for (cnt = 0; cnt < sizeof(fw->risc_gp_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			printk("\n");
+
+		printk("%08x ", fw->risc_gp_reg[cnt]);
+	}
+
+	printk("\n\nShadow Registers");
+	for (cnt = 0; cnt < sizeof(fw->shadow_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			printk("\n");
+
+		printk("%08x ", fw->shadow_reg[cnt]);
+	}
+
+	printk("\n\nLMC Registers");
+	for (cnt = 0; cnt < sizeof(fw->lmc_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			printk("\n");
+
+		printk("%08x ", fw->lmc_reg[cnt]);
+	}
+
+	printk("\n\nFPM Hardware Registers");
+	for (cnt = 0; cnt < sizeof(fw->fpm_hdw_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			printk("\n");
+
+		printk("%08x ", fw->fpm_hdw_reg[cnt]);
+	}
+
+	printk("\n\nFB Hardware Registers");
+	for (cnt = 0; cnt < sizeof(fw->fb_hdw_reg) / 4; cnt++) {
+		if (cnt % 8 == 0)
+			printk("\n");
+
+		printk("%08x ", fw->fb_hdw_reg[cnt]);
+	}
+
+	printk("\n\nCode RAM");
+	for (cnt = 0; cnt < sizeof (fw->code_ram) / 4; cnt++) {
+		if (cnt % 8 == 0) {
+			printk("\n%08x: ", cnt + 0x20000);
+		}
+		printk("%08x ", fw->code_ram[cnt]);
+	}
+
+	printk("\n\nExternal Memory");
+	ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1;
+	for (cnt = 0; cnt < ext_mem_cnt; cnt++) {
+		if (cnt % 8 == 0) {
+			printk("\n%08x: ", cnt + 0x100000);
+		}
+		printk("%08x ", fw->ext_mem[cnt]);
+	}
+
+	printk("\n[<==END] ISP Debug Dump");
+}
+
 //FIXME
 
 /****************************************************************************/

@@ -1066,6 +2245,21 @@ qla2x00_print_scsi_cmd(struct scsi_cmnd 
 	printk("  state=%d\n", sp->state);
 }
 
+void
+qla2x00_dump_pkt(void *pkt)
+{
+	uint32_t i;
+	uint8_t *data = (uint8_t *) pkt;
+
+	for (i = 0; i < 64; i++) {
+		if (!(i % 4))
+			printk("\n%02x: ", i);
+
+		printk("%02x ", data[i]);
+	}
+	printk("\n");
+}
+
 #if defined(QL_DEBUG_ROUTINES)
 /*
  * qla2x00_formatted_dump_buffer

@@ -230,4 +230,36 @@ struct qla2100_fw_dump {
 	uint16_t risc_ram[0xf000];
 };
 
+#define FW_DUMP_SIZE_24XX	0x2B0000
 
+struct qla24xx_fw_dump {
+	uint32_t hccr;
+	uint32_t host_reg[32];
+	uint16_t mailbox_reg[32];
+	uint32_t xseq_gp_reg[128];
+	uint32_t xseq_0_reg[16];
+	uint32_t xseq_1_reg[16];
+	uint32_t rseq_gp_reg[128];
+	uint32_t rseq_0_reg[16];
+	uint32_t rseq_1_reg[16];
+	uint32_t rseq_2_reg[16];
+	uint32_t cmd_dma_reg[16];
+	uint32_t req0_dma_reg[15];
+	uint32_t resp0_dma_reg[15];
+	uint32_t req1_dma_reg[15];
+	uint32_t xmt0_dma_reg[32];
+	uint32_t xmt1_dma_reg[32];
+	uint32_t xmt2_dma_reg[32];
+	uint32_t xmt3_dma_reg[32];
+	uint32_t xmt4_dma_reg[32];
+	uint32_t xmt_data_dma_reg[16];
+	uint32_t rcvt0_data_dma_reg[32];
+	uint32_t rcvt1_data_dma_reg[32];
+	uint32_t risc_gp_reg[128];
+	uint32_t shadow_reg[7];
+	uint32_t lmc_reg[112];
+	uint32_t fpm_hdw_reg[192];
+	uint32_t fb_hdw_reg[176];
+	uint32_t code_ram[0x2000];
+	uint32_t ext_mem[1];
+};

@@ -198,11 +198,14 @@ extern void qla2x00_write_nvram_word(scs
  */
 extern void qla2100_fw_dump(scsi_qla_host_t *, int);
 extern void qla2300_fw_dump(scsi_qla_host_t *, int);
+extern void qla24xx_fw_dump(scsi_qla_host_t *, int);
 extern void qla2100_ascii_fw_dump(scsi_qla_host_t *);
 extern void qla2300_ascii_fw_dump(scsi_qla_host_t *);
+extern void qla24xx_ascii_fw_dump(scsi_qla_host_t *);
 extern void qla2x00_dump_regs(scsi_qla_host_t *);
 extern void qla2x00_dump_buffer(uint8_t *, uint32_t);
 extern void qla2x00_print_scsi_cmd(struct scsi_cmnd *);
+extern void qla2x00_dump_pkt(void *);
 
 /*
  * Global Function Prototypes in qla_gs.c source file.

@@ -21,12 +21,19 @@
 static inline ms_iocb_entry_t *
 qla2x00_prep_ms_iocb(scsi_qla_host_t *, uint32_t, uint32_t);
 
+static inline void *
+qla24xx_prep_ms_iocb(scsi_qla_host_t *, uint32_t, uint32_t);
+
 static inline struct ct_sns_req *
 qla2x00_prep_ct_req(struct ct_sns_req *, uint16_t, uint16_t);
 
 static inline struct sns_cmd_pkt *
 qla2x00_prep_sns_cmd(scsi_qla_host_t *, uint16_t, uint16_t, uint16_t);
 
+static int
+qla2x00_chk_ms_status(scsi_qla_host_t *, ms_iocb_entry_t *, struct ct_sns_rsp *,
+    const char *);
+
 static int qla2x00_sns_ga_nxt(scsi_qla_host_t *, fc_port_t *);
 static int qla2x00_sns_gid_pt(scsi_qla_host_t *, sw_info_t *);
 static int qla2x00_sns_gpn_id(scsi_qla_host_t *, sw_info_t *);

@@ -34,8 +41,9 @@ static int qla2x00_sns_gnn_id(scsi_qla_h
 static int qla2x00_sns_rft_id(scsi_qla_host_t *);
 static int qla2x00_sns_rnn_id(scsi_qla_host_t *);
 
+
 /**
- * qla2x00_prep_ms_iocb() - Prepare common MS IOCB fields for SNS CT query.
+ * qla2x00_prep_ms_iocb() - Prepare common MS/CT IOCB fields for SNS CT query.
  * @ha: HA context
  * @req_size: request size in bytes
  * @rsp_size: response size in bytes

@@ -47,6 +55,9 @@ qla2x00_prep_ms_iocb(scsi_qla_host_t *ha
 {
 	ms_iocb_entry_t *ms_pkt;
 
+	if (IS_QLA24XX(ha) || IS_QLA25XX(ha))
+		return qla24xx_prep_ms_iocb(ha, req_size, rsp_size);
+
 	ms_pkt = ha->ms_iocb;
 	memset(ms_pkt, 0, sizeof(ms_iocb_entry_t));
 

@@ -72,6 +83,42 @@ qla2x00_prep_ms_iocb(scsi_qla_host_t *ha
 }
 
 /**
+ * qla24xx_prep_ms_iocb() - Prepare common CT IOCB fields for SNS CT query.
+ * @ha: HA context
+ * @req_size: request size in bytes
+ * @rsp_size: response size in bytes
+ *
+ * Returns a pointer to the @ha's ms_iocb.
+ */
+static inline void *
+qla24xx_prep_ms_iocb(scsi_qla_host_t *ha, uint32_t req_size, uint32_t rsp_size)
+{
+	struct ct_entry_24xx *ct_pkt;
+
+	ct_pkt = (struct ct_entry_24xx *)ha->ms_iocb;
+	memset(ct_pkt, 0, sizeof(struct ct_entry_24xx));
+
+	ct_pkt->entry_type = CT_IOCB_TYPE;
+	ct_pkt->entry_count = 1;
+	ct_pkt->nport_handle = __constant_cpu_to_le16(NPH_SNS);
+	ct_pkt->timeout = __constant_cpu_to_le16(25);
+	ct_pkt->cmd_dsd_count = __constant_cpu_to_le16(1);
+	ct_pkt->rsp_dsd_count = __constant_cpu_to_le16(1);
+	ct_pkt->rsp_byte_count = cpu_to_le32(rsp_size);
+	ct_pkt->cmd_byte_count = cpu_to_le32(req_size);
+
+	ct_pkt->dseg_0_address[0] = cpu_to_le32(LSD(ha->ct_sns_dma));
+	ct_pkt->dseg_0_address[1] = cpu_to_le32(MSD(ha->ct_sns_dma));
+	ct_pkt->dseg_0_len = ct_pkt->cmd_byte_count;
+
+	ct_pkt->dseg_1_address[0] = cpu_to_le32(LSD(ha->ct_sns_dma));
+	ct_pkt->dseg_1_address[1] = cpu_to_le32(MSD(ha->ct_sns_dma));
+	ct_pkt->dseg_1_len = ct_pkt->rsp_byte_count;
+
+	return (ct_pkt);
+}
+
+/**
  * qla2x00_prep_ct_req() - Prepare common CT request fields for SNS query.
  * @ct_req: CT request buffer
  * @cmd: GS command

@@ -93,6 +140,47 @@ qla2x00_prep_ct_req(struct ct_sns_req *c
 	return (ct_req);
 }
 
+static int
+qla2x00_chk_ms_status(scsi_qla_host_t *ha, ms_iocb_entry_t *ms_pkt,
+    struct ct_sns_rsp *ct_rsp, const char *routine)
+{
+	int rval;
+	uint16_t comp_status;
+
+	rval = QLA_FUNCTION_FAILED;
+	if (ms_pkt->entry_status != 0) {
+		DEBUG2_3(printk("scsi(%ld): %s failed, error status (%x).\n",
+		    ha->host_no, routine, ms_pkt->entry_status));
+	} else {
+		if (IS_QLA24XX(ha) || IS_QLA25XX(ha))
+			comp_status =
+			    ((struct ct_entry_24xx *)ms_pkt)->comp_status;
+		else
+			comp_status = le16_to_cpu(ms_pkt->status);
+		switch (comp_status) {
+		case CS_COMPLETE:
+		case CS_DATA_UNDERRUN:
+		case CS_DATA_OVERRUN:		/* Overrun? */
+			if (ct_rsp->header.response !=
+			    __constant_cpu_to_be16(CT_ACCEPT_RESPONSE)) {
+				DEBUG2_3(printk("scsi(%ld): %s failed, "
+				    "rejected request:\n", ha->host_no,
+				    routine));
+				DEBUG2_3(qla2x00_dump_buffer(
+				    (uint8_t *)&ct_rsp->header,
+				    sizeof(struct ct_rsp_hdr)));
+			} else
+				rval = QLA_SUCCESS;
+			break;
+		default:
+			DEBUG2_3(printk("scsi(%ld): %s failed, completion "
+			    "status (%x).\n", ha->host_no, routine,
+			    comp_status));
+			break;
+		}
+	}
+	return rval;
+}
 
 /**
  * qla2x00_ga_nxt() - SNS scan for fabric devices via GA_NXT command.

@@ -135,12 +223,8 @@ qla2x00_ga_nxt(scsi_qla_host_t *ha, fc_p
 		/*EMPTY*/
 		DEBUG2_3(printk("scsi(%ld): GA_NXT issue IOCB failed (%d).\n",
 		    ha->host_no, rval));
-	} else if (ct_rsp->header.response !=
-	    __constant_cpu_to_be16(CT_ACCEPT_RESPONSE)) {
-		DEBUG2_3(printk("scsi(%ld): GA_NXT failed, rejected request, "
-		    "ga_nxt_rsp:\n", ha->host_no));
-		DEBUG2_3(qla2x00_dump_buffer((uint8_t *)&ct_rsp->header,
-		    sizeof(struct ct_rsp_hdr)));
+	} else if (qla2x00_chk_ms_status(ha, ms_pkt, ct_rsp, "GA_NXT") !=
+	    QLA_SUCCESS) {
 		rval = QLA_FUNCTION_FAILED;
 	} else {
 		/* Populate fc_port_t entry. */

@@ -223,12 +307,8 @@ qla2x00_gid_pt(scsi_qla_host_t *ha, sw_i
 		/*EMPTY*/
 		DEBUG2_3(printk("scsi(%ld): GID_PT issue IOCB failed (%d).\n",
 		    ha->host_no, rval));
-	} else if (ct_rsp->header.response !=
-	    __constant_cpu_to_be16(CT_ACCEPT_RESPONSE)) {
-		DEBUG2_3(printk("scsi(%ld): GID_PT failed, rejected request, "
-		    "gid_pt_rsp:\n", ha->host_no));
-		DEBUG2_3(qla2x00_dump_buffer((uint8_t *)&ct_rsp->header,
-		    sizeof(struct ct_rsp_hdr)));
+	} else if (qla2x00_chk_ms_status(ha, ms_pkt, ct_rsp, "GID_PT") !=
+	    QLA_SUCCESS) {
 		rval = QLA_FUNCTION_FAILED;
 	} else {
 		/* Set port IDs in switch info list. */

@@ -302,12 +382,8 @@ qla2x00_gpn_id(scsi_qla_host_t *ha, sw_i
 			/*EMPTY*/
 			DEBUG2_3(printk("scsi(%ld): GPN_ID issue IOCB failed "
 			    "(%d).\n", ha->host_no, rval));
-		} else if (ct_rsp->header.response !=
-		    __constant_cpu_to_be16(CT_ACCEPT_RESPONSE)) {
-			DEBUG2_3(printk("scsi(%ld): GPN_ID failed, rejected "
-			    "request, gpn_id_rsp:\n", ha->host_no));
-			DEBUG2_3(qla2x00_dump_buffer((uint8_t *)&ct_rsp->header,
-			    sizeof(struct ct_rsp_hdr)));
+		} else if (qla2x00_chk_ms_status(ha, ms_pkt, ct_rsp,
+		    "GPN_ID") != QLA_SUCCESS) {
 			rval = QLA_FUNCTION_FAILED;
 		} else {
 			/* Save portname */

@@ -367,12 +443,8 @@ qla2x00_gnn_id(scsi_qla_host_t *ha, sw_i
 			/*EMPTY*/
 			DEBUG2_3(printk("scsi(%ld): GNN_ID issue IOCB failed "
 			    "(%d).\n", ha->host_no, rval));
-		} else if (ct_rsp->header.response !=
-		    __constant_cpu_to_be16(CT_ACCEPT_RESPONSE)) {
-			DEBUG2_3(printk("scsi(%ld): GNN_ID failed, rejected "
-			    "request, gnn_id_rsp:\n", ha->host_no));
-			DEBUG2_3(qla2x00_dump_buffer((uint8_t *)&ct_rsp->header,
-			    sizeof(struct ct_rsp_hdr)));
+		} else if (qla2x00_chk_ms_status(ha, ms_pkt, ct_rsp,
+		    "GNN_ID") != QLA_SUCCESS) {
 			rval = QLA_FUNCTION_FAILED;
 		} else {
 			/* Save nodename */

@@ -446,12 +518,8 @@ qla2x00_rft_id(scsi_qla_host_t *ha)
 		/*EMPTY*/
 		DEBUG2_3(printk("scsi(%ld): RFT_ID issue IOCB failed (%d).\n",
 		    ha->host_no, rval));
-	} else if (ct_rsp->header.response !=
-	    __constant_cpu_to_be16(CT_ACCEPT_RESPONSE)) {
-		DEBUG2_3(printk("scsi(%ld): RFT_ID failed, rejected "
-		    "request, rft_id_rsp:\n", ha->host_no));
-		DEBUG2_3(qla2x00_dump_buffer((uint8_t *)&ct_rsp->header,
-		    sizeof(struct ct_rsp_hdr)));
+	} else if (qla2x00_chk_ms_status(ha, ms_pkt, ct_rsp, "RFT_ID") !=
+	    QLA_SUCCESS) {
 		rval = QLA_FUNCTION_FAILED;
 	} else {
 		DEBUG2(printk("scsi(%ld): RFT_ID exiting normally.\n",

@@ -505,12 +573,8 @@ qla2x00_rff_id(scsi_qla_host_t *ha)
 		/*EMPTY*/
 		DEBUG2_3(printk("scsi(%ld): RFF_ID issue IOCB failed (%d).\n",
 		    ha->host_no, rval));
-	} else if (ct_rsp->header.response !=
-	    __constant_cpu_to_be16(CT_ACCEPT_RESPONSE)) {
-		DEBUG2_3(printk("scsi(%ld): RFF_ID failed, rejected "
-		    "request, rff_id_rsp:\n", ha->host_no));
-		DEBUG2_3(qla2x00_dump_buffer((uint8_t *)&ct_rsp->header,
-		    sizeof(struct ct_rsp_hdr)));
+	} else if (qla2x00_chk_ms_status(ha, ms_pkt, ct_rsp, "RFF_ID") !=
+	    QLA_SUCCESS) {
 		rval = QLA_FUNCTION_FAILED;
 	} else {
 		DEBUG2(printk("scsi(%ld): RFF_ID exiting normally.\n",

@@ -553,7 +617,7 @@ qla2x00_rnn_id(scsi_qla_host_t *ha)
 	ct_req->req.rnn_id.port_id[1] = ha->d_id.b.area;
 	ct_req->req.rnn_id.port_id[2] = ha->d_id.b.al_pa;
 
-	memcpy(ct_req->req.rnn_id.node_name, ha->init_cb->node_name, WWN_SIZE);
+	memcpy(ct_req->req.rnn_id.node_name, ha->node_name, WWN_SIZE);
 
 	/* Execute MS IOCB */
 	rval = qla2x00_issue_iocb(ha, ha->ms_iocb, ha->ms_iocb_dma,

@@ -562,12 +626,8 @@ qla2x00_rnn_id(scsi_qla_host_t *ha)
 		/*EMPTY*/
 		DEBUG2_3(printk("scsi(%ld): RNN_ID issue IOCB failed (%d).\n",
 		    ha->host_no, rval));
-	} else if (ct_rsp->header.response !=
-	    __constant_cpu_to_be16(CT_ACCEPT_RESPONSE)) {
-		DEBUG2_3(printk("scsi(%ld): RNN_ID failed, rejected "
-		    "request, rnn_id_rsp:\n", ha->host_no));
-		DEBUG2_3(qla2x00_dump_buffer((uint8_t *)&ct_rsp->header,
-		    sizeof(struct ct_rsp_hdr)));
+	} else if (qla2x00_chk_ms_status(ha, ms_pkt, ct_rsp, "RNN_ID") !=
+	    QLA_SUCCESS) {
 		rval = QLA_FUNCTION_FAILED;
 	} else {
 		DEBUG2(printk("scsi(%ld): RNN_ID exiting normally.\n",

@@ -611,7 +671,7 @@ qla2x00_rsnn_nn(scsi_qla_host_t *ha)
 	ct_rsp = &ha->ct_sns->p.rsp;
 
 	/* Prepare CT arguments -- node_name, symbolic node_name, size */
-	memcpy(ct_req->req.rsnn_nn.node_name, ha->init_cb->node_name, WWN_SIZE);
+	memcpy(ct_req->req.rsnn_nn.node_name, ha->node_name, WWN_SIZE);
 	
 	/* Prepare the Symbolic Node Name */
 	/* Board type */

@@ -641,12 +701,8 @@ qla2x00_rsnn_nn(scsi_qla_host_t *ha)
 		/*EMPTY*/
 		DEBUG2_3(printk("scsi(%ld): RSNN_NN issue IOCB failed (%d).\n",
 		    ha->host_no, rval));
-	} else if (ct_rsp->header.response !=
-	    __constant_cpu_to_be16(CT_ACCEPT_RESPONSE)) {
-		DEBUG2_3(printk("scsi(%ld): RSNN_NN failed, rejected "
-		    "request, rsnn_id_rsp:\n", ha->host_no));
-		DEBUG2_3(qla2x00_dump_buffer((uint8_t *)&ct_rsp->header,
-		    sizeof(struct ct_rsp_hdr)));
+	} else if (qla2x00_chk_ms_status(ha, ms_pkt, ct_rsp, "RSNN_NN") !=
+	    QLA_SUCCESS) {
 		rval = QLA_FUNCTION_FAILED;
 	} else {
 		DEBUG2(printk("scsi(%ld): RSNN_NN exiting normally.\n",

@@ -1028,14 +1084,14 @@ qla2x00_sns_rnn_id(scsi_qla_host_t *ha)
 	sns_cmd->p.cmd.param[1] = ha->d_id.b.area;
 	sns_cmd->p.cmd.param[2] = ha->d_id.b.domain;
 
-	sns_cmd->p.cmd.param[4] = ha->init_cb->node_name[7];
-	sns_cmd->p.cmd.param[5] = ha->init_cb->node_name[6];
-	sns_cmd->p.cmd.param[6] = ha->init_cb->node_name[5];
-	sns_cmd->p.cmd.param[7] = ha->init_cb->node_name[4];
-	sns_cmd->p.cmd.param[8] = ha->init_cb->node_name[3];
-	sns_cmd->p.cmd.param[9] = ha->init_cb->node_name[2];
-	sns_cmd->p.cmd.param[10] = ha->init_cb->node_name[1];
-	sns_cmd->p.cmd.param[11] = ha->init_cb->node_name[0];
+	sns_cmd->p.cmd.param[4] = ha->node_name[7];
+	sns_cmd->p.cmd.param[5] = ha->node_name[6];
+	sns_cmd->p.cmd.param[6] = ha->node_name[5];
+	sns_cmd->p.cmd.param[7] = ha->node_name[4];
+	sns_cmd->p.cmd.param[8] = ha->node_name[3];
+	sns_cmd->p.cmd.param[9] = ha->node_name[2];
+	sns_cmd->p.cmd.param[10] = ha->node_name[1];
+	sns_cmd->p.cmd.param[11] = ha->node_name[0];
 
 	/* Execute SNS command. */
 	rval = qla2x00_send_sns(ha, ha->sns_cmd_dma, RNN_ID_SNS_CMD_SIZE / 2,

@@ -95,10 +95,10 @@ extern int
 qla2x00_load_ram(scsi_qla_host_t *, dma_addr_t, uint16_t, uint16_t);
 
 extern int
-qla2x00_load_ram_ext(scsi_qla_host_t *, dma_addr_t, uint32_t, uint16_t);
+qla2x00_load_ram_ext(scsi_qla_host_t *, dma_addr_t, uint32_t, uint32_t);
 
 extern int
-qla2x00_execute_fw(scsi_qla_host_t *);
+qla2x00_execute_fw(scsi_qla_host_t *, uint32_t);
 
 extern void
 qla2x00_get_fw_version(scsi_qla_host_t *, uint16_t *,

@@ -114,7 +114,7 @@ extern int
 qla2x00_mbx_reg_test(scsi_qla_host_t *);
 
 extern int
-qla2x00_verify_checksum(scsi_qla_host_t *);
+qla2x00_verify_checksum(scsi_qla_host_t *, uint32_t);
 
 extern int
 qla2x00_issue_iocb(scsi_qla_host_t *, void *, dma_addr_t, size_t);

@@ -124,7 +124,7 @@ qla2x00_abort_command(scsi_qla_host_t *,
 
 #if USE_ABORT_TGT
 extern int
-qla2x00_abort_target(fc_port_t *fcport);
+qla2x00_abort_target(fc_port_t *);
 #endif
 
 extern int

@@ -163,7 +163,7 @@ extern int
 qla2x00_login_local_device(scsi_qla_host_t *, uint16_t, uint16_t *, uint8_t);
 
 extern int
-qla2x00_fabric_logout(scsi_qla_host_t *ha, uint16_t loop_id);
+qla2x00_fabric_logout(scsi_qla_host_t *, uint16_t, uint8_t, uint8_t, uint8_t);
 
 extern int
 qla2x00_full_login_lip(scsi_qla_host_t *ha);

@@ -178,6 +178,15 @@ qla2x00_get_resource_cnts(scsi_qla_host_
 extern int
 qla2x00_get_fcal_position_map(scsi_qla_host_t *ha, char *pos_map);
 
+extern int qla2x00_system_error(scsi_qla_host_t *);
+
+extern int
+qla2x00_get_serdes_params(scsi_qla_host_t *, uint16_t *, uint16_t *,
+    uint16_t *);
+
+extern int
+qla2x00_set_serdes_params(scsi_qla_host_t *, uint16_t, uint16_t, uint16_t);
+
 /*
  * Global Function Prototypes in qla_isr.c source file.
  */

1,393 lines not on this page · raw message

@@ -121,23 +121,15 @@ qla2x00_sysfs_read_nvram(struct kobject 
 {
 	struct scsi_qla_host *ha = to_qla_host(dev_to_shost(container_of(kobj,
 	    struct device, kobj)));
-	uint16_t	*witer;
 	unsigned long	flags;
-	uint16_t	cnt;
 
-	if (!capable(CAP_SYS_ADMIN) || off != 0 || count != sizeof(nvram_t))
+	if (!capable(CAP_SYS_ADMIN) || off != 0 || count != ha->nvram_size)
 		return 0;
 
 	/* Read NVRAM. */
 	spin_lock_irqsave(&ha->hardware_lock, flags);
-	qla2x00_lock_nvram_access(ha);
- 	witer = (uint16_t *)buf;
- 	for (cnt = 0; cnt < count / 2; cnt++) {
-		*witer = cpu_to_le16(qla2x00_get_nvram_word(ha,
-		    cnt+ha->nvram_base));
-		witer++;
- 	}
-	qla2x00_unlock_nvram_access(ha);
+	qla2x00_read_nvram_data(ha, (uint8_t *)buf, ha->nvram_base,
+	    ha->nvram_size);
 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
 
 	return (count);

@@ -149,34 +141,38 @@ qla2x00_sysfs_write_nvram(struct kobject
 {
 	struct scsi_qla_host *ha = to_qla_host(dev_to_shost(container_of(kobj,
 	    struct device, kobj)));
-	uint8_t		*iter;
-	uint16_t	*witer;
 	unsigned long	flags;
 	uint16_t	cnt;
-	uint8_t		chksum;
 
-	if (!capable(CAP_SYS_ADMIN) || off != 0 || count != sizeof(nvram_t))
+	if (!capable(CAP_SYS_ADMIN) || off != 0 || count != ha->nvram_size)
 		return 0;
 
 	/* Checksum NVRAM. */
-	iter = (uint8_t *)buf;
-	chksum = 0;
-	for (cnt = 0; cnt < count - 1; cnt++)
-		chksum += *iter++;
-	chksum = ~chksum + 1;
-	*iter = chksum;
+	if (IS_QLA24XX(ha) || IS_QLA25XX(ha)) {
+		uint32_t *iter;
+		uint32_t chksum;
+
+		iter = (uint32_t *)buf;
+		chksum = 0;
+		for (cnt = 0; cnt < ((count >> 2) - 1); cnt++)
+			chksum += le32_to_cpu(*iter++);
+		chksum = ~chksum + 1;
+		*iter = cpu_to_le32(chksum);
+	} else {
+		uint8_t *iter;
+		uint8_t chksum;
+
+		iter = (uint8_t *)buf;
+		chksum = 0;
+		for (cnt = 0; cnt < count - 1; cnt++)
+			chksum += *iter++;
+		chksum = ~chksum + 1;
+		*iter = chksum;
+	}
 
 	/* Write NVRAM. */
 	spin_lock_irqsave(&ha->hardware_lock, flags);
-	qla2x00_lock_nvram_access(ha);
-	qla2x00_release_nvram_protection(ha);
- 	witer = (uint16_t *)buf;
-	for (cnt = 0; cnt < count / 2; cnt++) {
-		qla2x00_write_nvram_word(ha, cnt+ha->nvram_base,
-		    cpu_to_le16(*witer));
-		witer++;
-	}
-	qla2x00_unlock_nvram_access(ha);
+	qla2x00_write_nvram_data(ha, (uint8_t *)buf, ha->nvram_base, count);
 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
 
 	return (count);

@@ -188,7 +184,7 @@ static struct bin_attribute sysfs_nvram_
 		.mode = S_IRUSR | S_IWUSR,
 		.owner = THIS_MODULE,
 	},
-	.size = sizeof(nvram_t),
+	.size = 0;
 	.read = qla2x00_sysfs_read_nvram,
 	.write = qla2x00_sysfs_write_nvram,
 };

@@ -199,6 +195,7 @@ qla2x00_alloc_sysfs_attr(scsi_qla_host_t
 	struct Scsi_Host *host = ha->host;
 
 	sysfs_create_bin_file(&host->shost_gendev.kobj, &sysfs_fw_dump_attr);
+	sysfs_nvram_attr.size = ha->nvram_size;
 	sysfs_create_bin_file(&host->shost_gendev.kobj, &sysfs_nvram_attr);
 }
 

@@ -202,6 +202,13 @@ extern void qla2x00_unlock_nvram_access(
 extern void qla2x00_release_nvram_protection(scsi_qla_host_t *);
 extern uint16_t qla2x00_get_nvram_word(scsi_qla_host_t *, uint32_t);
 extern void qla2x00_write_nvram_word(scsi_qla_host_t *, uint32_t, uint16_t);
+extern uint8_t *qla2x00_read_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t,
+    uint32_t);
+extern int qla2x00_write_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t,
+    uint32_t);
+extern uint32_t *qla24xx_read_flash_data(scsi_qla_host_t *, uint32_t *,
+    uint32_t, uint32_t);
+
 /*
  * Global Function Prototypes in qla_dbg.c source file.
  */

549 lines not on this page · raw message

@@ -85,6 +85,7 @@ extern uint16_t qla2x00_calc_iocbs_64(ui
 extern void qla2x00_build_scsi_iocbs_32(srb_t *, cmd_entry_t *, uint16_t);
 extern void qla2x00_build_scsi_iocbs_64(srb_t *, cmd_entry_t *, uint16_t);
 extern int qla2x00_start_scsi(srb_t *sp);
+extern int qla24xx_start_scsi(srb_t *sp);
 int qla2x00_marker(scsi_qla_host_t *, uint16_t, uint16_t, uint8_t);
 int __qla2x00_marker(scsi_qla_host_t *, uint16_t, uint16_t, uint8_t);
 

380 lines not on this page · raw message

@@ -193,6 +193,7 @@ qla2x00_set_serdes_params(scsi_qla_host_
  */
 extern irqreturn_t qla2100_intr_handler(int, void *, struct pt_regs *);
 extern irqreturn_t qla2300_intr_handler(int, void *, struct pt_regs *);
+extern irqreturn_t qla24xx_intr_handler(int, void *, struct pt_regs *);
 extern void qla2x00_process_response_queue(struct scsi_qla_host *);
 
 /*

@@ -119,8 +119,10 @@ qla2x00_poll(scsi_qla_host_t *ha)
 {
 	if (IS_QLA2100(ha) || IS_QLA2200(ha))
 		qla2100_intr_handler(0, ha, NULL);
-	else
+	else if (IS_QLA23XX(ha))
 		qla2300_intr_handler(0, ha, NULL);
+	else
+		qla24xx_intr_handler(0, ha, NULL);
 }
 
 

@@ -132,12 +134,18 @@ qla2x00_enable_intrs(scsi_qla_host_t *ha
 {
 	unsigned long flags = 0;
 	device_reg_t __iomem *reg = ha->iobase;
+	struct device_reg_24xx __iomem *reg24;
 
 	spin_lock_irqsave(&ha->hardware_lock, flags);
+	if (IS_QLA24XX(ha) || IS_QLA25XX(ha)) {
+		reg24 = (struct device_reg_24xx __iomem *)ha->iobase;
+		WRT_REG_DWORD(&reg24->ictrl, ICRX_EN_RISC_INT);
+		RD_REG_DWORD(&reg24->ictrl);
+	} else {
+		WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
+		RD_REG_WORD(&reg->ictrl);
+	}
 	ha->interrupts_on = 1;
-	/* enable risc and host interrupts */
-	WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
-	RD_REG_WORD(&reg->ictrl);
 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
 
 }

@@ -147,12 +155,19 @@ qla2x00_disable_intrs(scsi_qla_host_t *h
 {
 	unsigned long flags = 0;
 	device_reg_t __iomem *reg = ha->iobase;
+	struct device_reg_24xx __iomem *reg24;
 
 	spin_lock_irqsave(&ha->hardware_lock, flags);
 	ha->interrupts_on = 0;
-	/* disable risc and host interrupts */
-	WRT_REG_WORD(&reg->ictrl, 0);
-	RD_REG_WORD(&reg->ictrl);
+	if (IS_QLA24XX(ha) || IS_QLA25XX(ha)) {
+		reg24 = (struct device_reg_24xx __iomem *)ha->iobase;
+		WRT_REG_DWORD(&reg24->ictrl, 0);
+		RD_REG_DWORD(&reg24->ictrl);
+
+	} else {
+		WRT_REG_WORD(&reg->ictrl, 0);
+		RD_REG_WORD(&reg->ictrl);
+	}
 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
 }
 

963 lines not on this page · raw message

@@ -63,23 +63,29 @@ qla2x00_sysfs_write_fw_dump(struct kobje
 			    ha->host_no);
 
 			vfree(ha->fw_dump_buffer);
-			free_pages((unsigned long)ha->fw_dump,
-			    ha->fw_dump_order);
+			if (!IS_QLA24XX(ha) && !IS_QLA25XX(ha))
+				free_pages((unsigned long)ha->fw_dump,
+				    ha->fw_dump_order);
 
 			ha->fw_dump_reading = 0;
 			ha->fw_dump_buffer = NULL;
 			ha->fw_dump = NULL;
+			ha->fw_dumped = 0;
 		}
 		break;
 	case 1:
-		if (ha->fw_dump != NULL && !ha->fw_dump_reading) {
+		if ((ha->fw_dump || ha->fw_dumped) && !ha->fw_dump_reading) {
 			ha->fw_dump_reading = 1;
 
-			dump_size = FW_DUMP_SIZE_1M;
-			if (ha->fw_memory_size < 0x20000) 
-				dump_size = FW_DUMP_SIZE_128K;
-			else if (ha->fw_memory_size < 0x80000) 
-				dump_size = FW_DUMP_SIZE_512K;
+			if (IS_QLA24XX(ha) || IS_QLA25XX(ha))
+				dump_size = FW_DUMP_SIZE_24XX;
+			else {
+				dump_size = FW_DUMP_SIZE_1M;
+				if (ha->fw_memory_size < 0x20000)
+					dump_size = FW_DUMP_SIZE_128K;
+				else if (ha->fw_memory_size < 0x80000)
+					dump_size = FW_DUMP_SIZE_512K;
+			}
 			ha->fw_dump_buffer = (char *)vmalloc(dump_size);
 			if (ha->fw_dump_buffer == NULL) {
 				qla_printk(KERN_WARNING, ha,

@@ -94,9 +100,11 @@ qla2x00_sysfs_write_fw_dump(struct kobje
 			    ha->host_no);
 			memset(ha->fw_dump_buffer, 0, dump_size);
 			if (IS_QLA2100(ha) || IS_QLA2200(ha))
- 				qla2100_ascii_fw_dump(ha);
- 			else
- 				qla2300_ascii_fw_dump(ha);
+				qla2100_ascii_fw_dump(ha);
+			else if (IS_QLA23XX(ha))
+				qla2300_ascii_fw_dump(ha);
+			else if (IS_QLA24XX(ha) || IS_QLA25XX(ha))
+				qla24xx_ascii_fw_dump(ha);
 			ha->fw_dump_buffer_len = strlen(ha->fw_dump_buffer);
 		}
 		break;

@@ -184,7 +192,7 @@ static struct bin_attribute sysfs_nvram_
 		.mode = S_IRUSR | S_IWUSR,
 		.owner = THIS_MODULE,
 	},
-	.size = 0;
+	.size = 0,
 	.read = qla2x00_sysfs_read_nvram,
 	.write = qla2x00_sysfs_write_nvram,
 };

@@ -59,6 +59,7 @@ extern int ql2xplogiabsentdevice;
 extern int ql2xenablezio;
 extern int ql2xintrdelaytimer;
 extern int ql2xloginretrycount;
+extern int ql2xfwloadbin;
 
 extern void qla2x00_sp_compl(scsi_qla_host_t *, srb_t *);
 

1,423 lines not on this page · raw message

@@ -288,6 +288,27 @@ qla2x00_delete_timer_from_cmd(srb_t *sp)
 	}
 }
 
+static inline uint8_t *host_to_fcp_swap(uint8_t *, uint32_t);
+
+/**
+ * host_to_fcp_swap() - 
+ * @fcp: 
+ * @bsize: 
+ *
+ * Returns 
+ */
+static inline uint8_t *
+host_to_fcp_swap(uint8_t *fcp, uint32_t bsize)
+{
+	uint32_t *ifcp = (uint32_t *) fcp;
+	uint32_t *ofcp = (uint32_t *) fcp;
+	uint32_t iter = bsize >> 2;
+
+	for (; iter ; iter--)
+		*ofcp++ = swab32(*ifcp++);
+
+	return (fcp);
+}
 
 static inline int qla2x00_is_reserved_id(scsi_qla_host_t *, uint16_t);
 static inline int

414 lines not on this page · raw message

@@ -1,4 +1,4 @@
-#define QLA_MODEL_NAMES         0x32
+#define QLA_MODEL_NAMES         0x44
 
 /*
  * Adapter model names.

@@ -53,7 +53,25 @@ static char *qla2x00_model_name[QLA_MODE
 	" ",		/* 0x12e */
 	"QLA210",	/* 0x12f */
 	"EMC 250",	/* 0x130 */
-	"HP A7538A"	/* 0x131 */
+	"HP A7538A",	/* 0x131 */
+	"QLA210",	/* 0x132 */
+	"QLA2460",	/* 0x133 */
+	"QLA2462",	/* 0x134 */
+	"QMC2462",	/* 0x135 */
+	"QMC2462S",	/* 0x136 */
+	"QLE2460",	/* 0x137 */
+	"QLE2462",	/* 0x138 */
+	"QME2462",	/* 0x139 */
+	"QLA2440",	/* 0x13a */
+	"QLA2442",	/* 0x13b */
+	"QSM2442",	/* 0x13c */
+	"QSM2462",	/* 0x13d */
+	"QLE210",	/* 0x13e */
+	"QLE220",	/* 0x13f */
+	"QLA2460",	/* 0x140 */
+	"QLA2462",	/* 0x141 */
+	"QLE2460",	/* 0x142 */
+	"QLE2462"	/* 0x143 */
 };
 
 static char *qla2x00_model_desc[QLA_MODEL_NAMES] = {

@@ -78,8 +96,8 @@ static char *qla2x00_model_desc[QLA_MODE
 	" ",						/* 0x112 */
 	" ",						/* 0x113 */
 	" ",						/* 0x114 */
-	"133MHz PCI-X to 2Gb FC Single Channel",	/* 0x115 */
-	"133MHz PCI-X to 2Gb FC Dual Channel",		/* 0x116 */
+	"133MHz PCI-X to 2Gb FC, Single Channel",	/* 0x115 */
+	"133MHz PCI-X to 2Gb FC, Dual Channel",		/* 0x116 */
 	"PCI-Express to 2Gb FC, Single Channel",	/* 0x117 */
 	"PCI-Express to 2Gb FC, Dual Channel",		/* 0x118 */
 	"133MHz PCI-X to 2Gb FC Optical",		/* 0x119 */

@@ -106,5 +124,23 @@ static char *qla2x00_model_desc[QLA_MODE
 	" ",						/* 0x12e */
 	"133MHz PCI-X to 2Gb FC SFF",			/* 0x12f */
 	"133MHz PCI-X to 2Gb FC SFF",			/* 0x130 */
-	"HP 1p2g QLA2340"				/* 0x131 */
+	"HP 1p2g QLA2340",				/* 0x131 */
+	"133MHz PCI-X to 2Gb FC, Single Channel",	/* 0x132 */
+	"PCI-X 2.0 to 4Gb FC, Single Channel",		/* 0x133 */
+	"PCI-X 2.0 to 4Gb FC, Dual Channel",		/* 0x134 */
+	"IBM eServer BC 4Gb FC Expansion Card",		/* 0x135 */
+	"IBM eServer BC 4Gb FC Expansion Card SFF",	/* 0x136 */
+	"PCI-Express to 4Gb FC, Single Channel",	/* 0x137 */
+	"PCI-Express to 4Gb FC, Dual Channel",		/* 0x138 */
+	"Dell PCI-Express to 4Gb FC, Dual Channel",	/* 0x139 */
+	"PCI-X 1.0 to 4Gb FC, Single Channel",		/* 0x13a */
+	"PCI-X 1.0 to 4Gb FC, Dual Channel",		/* 0x13b */
+	"Server I/O Module 4Gb FC, Single Channel",	/* 0x13c */
+	"Server I/O Module 4Gb FC, Single Channel",	/* 0x13d */
+	"PCI-Express to 2Gb FC, Single Channel",	/* 0x13e */
+	"PCI-Express to 4Gb FC, Single Channel",	/* 0x13f */
+	"Sun PCI-X 2.0 to 4Gb FC, Single Channel",	/* 0x140 */
+	"Sun PCI-X 2.0 to 4Gb FC, Dual Channel",	/* 0x141 */
+	"Sun PCI-Express to 2Gb FC, Single Channel",	/* 0x142 */
+	"Sun PCI-Express to 4Gb FC, Single Channel"	/* 0x143 */
 };

@@ -74,7 +74,7 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int
 	fw->hccr = RD_REG_WORD(&reg->hccr);
 
 	/* Pause RISC. */
-	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC); 
+	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
 	if (IS_QLA2300(ha)) {
 		for (cnt = 30000;
 		    (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&

@@ -91,85 +91,85 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int
 
 	if (rval == QLA_SUCCESS) {
 		dmp_reg = (uint16_t __iomem *)(reg + 0);
-		for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
 			fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10);
-		for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
 			fw->risc_host_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x40);
-		for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
 			fw->mailbox_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
 		WRT_REG_WORD(&reg->ctrl_status, 0x40);
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
-		for (cnt = 0; cnt < sizeof(fw->resp_dma_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->resp_dma_reg) / 2; cnt++)
 			fw->resp_dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
 		WRT_REG_WORD(&reg->ctrl_status, 0x50);
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
-		for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
 			fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
 		WRT_REG_WORD(&reg->ctrl_status, 0x00);
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0);
-		for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
 			fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
-		WRT_REG_WORD(&reg->pcr, 0x2000); 
+		WRT_REG_WORD(&reg->pcr, 0x2000);
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
-		for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
 			fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
-		WRT_REG_WORD(&reg->pcr, 0x2200); 
+		WRT_REG_WORD(&reg->pcr, 0x2200);
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
-		for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
 			fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
-		WRT_REG_WORD(&reg->pcr, 0x2400); 
+		WRT_REG_WORD(&reg->pcr, 0x2400);
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
-		for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
 			fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
-		WRT_REG_WORD(&reg->pcr, 0x2600); 
+		WRT_REG_WORD(&reg->pcr, 0x2600);
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
-		for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
 			fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
-		WRT_REG_WORD(&reg->pcr, 0x2800); 
+		WRT_REG_WORD(&reg->pcr, 0x2800);
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
-		for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
 			fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
-		WRT_REG_WORD(&reg->pcr, 0x2A00); 
+		WRT_REG_WORD(&reg->pcr, 0x2A00);
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
-		for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
 			fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
-		WRT_REG_WORD(&reg->pcr, 0x2C00); 
+		WRT_REG_WORD(&reg->pcr, 0x2C00);
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
-		for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
 			fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
-		WRT_REG_WORD(&reg->pcr, 0x2E00); 
+		WRT_REG_WORD(&reg->pcr, 0x2E00);
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
-		for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
 			fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
-		WRT_REG_WORD(&reg->ctrl_status, 0x10); 
+		WRT_REG_WORD(&reg->ctrl_status, 0x10);
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
-		for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
 			fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
-		WRT_REG_WORD(&reg->ctrl_status, 0x20); 
+		WRT_REG_WORD(&reg->ctrl_status, 0x20);
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
-		for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
 			fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
-		WRT_REG_WORD(&reg->ctrl_status, 0x30); 
+		WRT_REG_WORD(&reg->ctrl_status, 0x30);
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
-		for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
 			fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
 		/* Reset RISC. */

@@ -622,7 +622,7 @@ qla2100_fw_dump(scsi_qla_host_t *ha, int
 	fw->hccr = RD_REG_WORD(&reg->hccr);
 
 	/* Pause RISC. */
-	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC); 
+	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
 	for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
 	    rval == QLA_SUCCESS; cnt--) {
 		if (cnt)

@@ -632,7 +632,7 @@ qla2100_fw_dump(scsi_qla_host_t *ha, int
 	}
 	if (rval == QLA_SUCCESS) {
 		dmp_reg = (uint16_t __iomem *)(reg + 0);
-		for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
 			fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10);

@@ -644,67 +644,67 @@ qla2100_fw_dump(scsi_qla_host_t *ha, int
 		}
 
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x20);
-		for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
 			fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
 		WRT_REG_WORD(&reg->ctrl_status, 0x00);
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0);
-		for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
 			fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
-		WRT_REG_WORD(&reg->pcr, 0x2000); 
+		WRT_REG_WORD(&reg->pcr, 0x2000);
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
-		for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
 			fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
-		WRT_REG_WORD(&reg->pcr, 0x2100); 
+		WRT_REG_WORD(&reg->pcr, 0x2100);
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
-		for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
 			fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
-		WRT_REG_WORD(&reg->pcr, 0x2200); 
+		WRT_REG_WORD(&reg->pcr, 0x2200);
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
-		for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
 			fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
-		WRT_REG_WORD(&reg->pcr, 0x2300); 
+		WRT_REG_WORD(&reg->pcr, 0x2300);
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
-		for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
 			fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
-		WRT_REG_WORD(&reg->pcr, 0x2400); 
+		WRT_REG_WORD(&reg->pcr, 0x2400);
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
-		for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
 			fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
-		WRT_REG_WORD(&reg->pcr, 0x2500); 
+		WRT_REG_WORD(&reg->pcr, 0x2500);
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
-		for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
 			fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
-		WRT_REG_WORD(&reg->pcr, 0x2600); 
+		WRT_REG_WORD(&reg->pcr, 0x2600);
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
-		for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
 			fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
-		WRT_REG_WORD(&reg->pcr, 0x2700); 
+		WRT_REG_WORD(&reg->pcr, 0x2700);
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
-		for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
 			fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
-		WRT_REG_WORD(&reg->ctrl_status, 0x10); 
+		WRT_REG_WORD(&reg->ctrl_status, 0x10);
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
-		for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
 			fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
-		WRT_REG_WORD(&reg->ctrl_status, 0x20); 
+		WRT_REG_WORD(&reg->ctrl_status, 0x20);
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
-		for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
 			fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
-		WRT_REG_WORD(&reg->ctrl_status, 0x30); 
+		WRT_REG_WORD(&reg->ctrl_status, 0x30);
 		dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
-		for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++) 
+		for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
 			fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++);
 
 		/* Reset the ISP. */

@@ -723,7 +723,7 @@ qla2100_fw_dump(scsi_qla_host_t *ha, int
 	if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
 	    (RD_REG_WORD(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) {
 
-		WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC); 
+		WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
 		for (cnt = 30000;
 		    (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
 		    rval == QLA_SUCCESS; cnt--) {