bcm1480 support
Subsystems (3)
cover bcm1480 support
This patch set against git changeset d1a2855c2190 adds support for the BCM1480 family of SiByte SoCs. The following are supported:
- BCM1255, BCM1280, BCM1455, BCM1480 dual and quad core chips
- 4 on-chip cache-coherent GigE MACs
- native PCI-X
- HT/PCI-X tunnel
- SMBus
as well as the usual assortment of flash, uarts, DDR DRAM, etc.
It also includes a sibyte headers update, some code cleanups, and a hack to work around a missing firmware feature.
-andy
PATCH 1/12 sibyte-fixes
Fix typo in cpu_probe_sibyte
Signed-off-by Andy Isaacson <[email protected]>
arch/mips/kernel/cpu-probe.c | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-)
arch/mips/kernel/cpu-probe.c +1 -1
@@ -618,7 +618,7 @@* cache code which eventually will be folded into c-r4k.c. Until * then we pretend it's got it's own cache architecture. */ - c->options &=MIPS_CPU_4K_CACHE ; + c->options &= ~MIPS_CPU_4K_CACHE ; c->options |=MIPS_CPU_SB1_CACHE ;switch (c->processor_id &0xff00 ) {
PATCH 2/12 1480-headers
In reply to Andrew IsaacsonAdd header files for BCM1480/1280/1455/1255 family of chips, and update sb1250 headers which are shared by BCM1480 family.
Signed-off-by Andy Isaacson <[email protected]>
include/asm-mips/sibyte/bcm1480_int.h | 310 ++++++++++ include/asm-mips/sibyte/bcm1480_l2c.h | 176 +++++ include/asm-mips/sibyte/bcm1480_mc.h | 962 ++++++++++++++++++++++++++++++++ include/asm-mips/sibyte/bcm1480_regs.h | 869 ++++++++++++++++++++++++++++ include/asm-mips/sibyte/bcm1480_scd.h | 436 ++++++++++++++ include/asm-mips/sibyte/sb1250.h | 11 include/asm-mips/sibyte/sb1250_defs.h | 33 - include/asm-mips/sibyte/sb1250_dma.h | 65 +- include/asm-mips/sibyte/sb1250_genbus.h | 225 +++++++ include/asm-mips/sibyte/sb1250_int.h | 6 include/asm-mips/sibyte/sb1250_l2c.h | 9 include/asm-mips/sibyte/sb1250_mac.h | 33 - include/asm-mips/sibyte/sb1250_mc.h | 4 include/asm-mips/sibyte/sb1250_regs.h | 33 - include/asm-mips/sibyte/sb1250_scd.h | 100 ++- include/asm-mips/sibyte/sb1250_smbus.h | 53 + include/asm-mips/sibyte/sb1250_uart.h | 11 17 files changed, 3237 insertions(+), 99 deletions(-)
include/asm-mips/sibyte/bcm1480_int.h new file +310 -0
@@ -0,0 +1,310 @@ +/* ********************************************************************* +* BCM1280/BCM1480 Board Support Package +* +* Interrupt Mapper definitions File: bcm1480_int.h +* +* This module contains constants for manipulating the +* BCM1255/BCM1280/BCM1455/BCM1480's interrupt mapper and +* definitions for the interrupt sources. +* +* BCM1480 specification level: 1X55_1X80-UM100-D4 (11/24/03) +* +********************************************************************* +* +* Copyright 2000,2001,2002,2003 +* Broadcom Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +********************************************************************* */ + + +#ifndef _BCM1480_INT_H +#define _BCM1480_INT_H + +#include "sb1250_defs.h" + +/* ********************************************************************* +* Interrupt Mapper Constants +********************************************************************* */ + +/* +* The interrupt mapper deals with 128-bit logical registers that are +* implemented as pairs of 64-bit registers, with the "low" 64 bits in +* a register that has an address 0x1000 higher(!) than the +* corresponding "high" register. +* +* For appropriate registers, bit 0 of the "high" register is a +* cascade bit that summarizes (as a bit-OR) the 64 bits of the "low" +* register. +*/ + +/* +* This entire file uses _BCM1480_ in all the symbols because it is +* entirely BCM1480 specific. +*/ + +/* +* Interrupt sources (Table 22) +*/ + +#define K_BCM1480_INT_SOURCES 128 + +#define _BCM1480_INT_HIGH (k) (k) +#define _BCM1480_INT_LOW (k) ((k)+64) + +#define K_BCM1480_INT_ADDR_TRAP _BCM1480_INT_HIGH(1) +#define K_BCM1480_INT_GPIO_0 _BCM1480_INT_HIGH(4) +#define K_BCM1480_INT_GPIO_1 _BCM1480_INT_HIGH(5) +#define K_BCM1480_INT_GPIO_2 _BCM1480_INT_HIGH(6) +#define K_BCM1480_INT_GPIO_3 _BCM1480_INT_HIGH(7) +#define K_BCM1480_INT_PCI_INTA _BCM1480_INT_HIGH(8) +#define K_BCM1480_INT_PCI_INTB _BCM1480_INT_HIGH(9) +#define K_BCM1480_INT_PCI_INTC _BCM1480_INT_HIGH(10) +#define K_BCM1480_INT_PCI_INTD _BCM1480_INT_HIGH(11) +#define K_BCM1480_INT_CYCLE_CP0 _BCM1480_INT_HIGH(12) +#define K_BCM1480_INT_CYCLE_CP1 _BCM1480_INT_HIGH(13) +#define K_BCM1480_INT_CYCLE_CP2 _BCM1480_INT_HIGH(14) +#define K_BCM1480_INT_CYCLE_CP3 _BCM1480_INT_HIGH(15) +#define K_BCM1480_INT_TIMER_0 _BCM1480_INT_HIGH(20) +#define K_BCM1480_INT_TIMER_1 _BCM1480_INT_HIGH(21) +#define K_BCM1480_INT_TIMER_2 _BCM1480_INT_HIGH(22) +#define K_BCM1480_INT_TIMER_3 _BCM1480_INT_HIGH(23) +#define K_BCM1480_INT_DM_CH_0 _BCM1480_INT_HIGH(28) +#define K_BCM1480_INT_DM_CH_1 _BCM1480_INT_HIGH(29) +#define K_BCM1480_INT_DM_CH_2 _BCM1480_INT_HIGH(30) +#define K_BCM1480_INT_DM_CH_3 _BCM1480_INT_HIGH(31) +#define K_BCM1480_INT_MAC_0 _BCM1480_INT_HIGH(36) +#define K_BCM1480_INT_MAC_0_CH1 _BCM1480_INT_HIGH(37) +#define K_BCM1480_INT_MAC_1 _BCM1480_INT_HIGH(38) +#define K_BCM1480_INT_MAC_1_CH1 _BCM1480_INT_HIGH(39) +#define K_BCM1480_INT_MAC_2 _BCM1480_INT_HIGH(40) +#define K_BCM1480_INT_MAC_2_CH1 _BCM1480_INT_HIGH(41) +#define K_BCM1480_INT_MAC_3 _BCM1480_INT_HIGH(42) +#define K_BCM1480_INT_MAC_3_CH1 _BCM1480_INT_HIGH(43) +#define K_BCM1480_INT_PMI_LOW _BCM1480_INT_HIGH(52) +#define K_BCM1480_INT_PMI_HIGH _BCM1480_INT_HIGH(53) +#define K_BCM1480_INT_PMO_LOW _BCM1480_INT_HIGH(54) +#define K_BCM1480_INT_PMO_HIGH _BCM1480_INT_HIGH(55) +#define K_BCM1480_INT_MBOX_0_0 _BCM1480_INT_HIGH(56) +#define K_BCM1480_INT_MBOX_0_1 _BCM1480_INT_HIGH(57) +#define K_BCM1480_INT_MBOX_0_2 _BCM1480_INT_HIGH(58) +#define K_BCM1480_INT_MBOX_0_3 _BCM1480_INT_HIGH(59) +#define K_BCM1480_INT_MBOX_1_0 _BCM1480_INT_HIGH(60) +#define K_BCM1480_INT_MBOX_1_1 _BCM1480_INT_HIGH(61) +#define K_BCM1480_INT_MBOX_1_2 _BCM1480_INT_HIGH(62) +#define K_BCM1480_INT_MBOX_1_3 _BCM1480_INT_HIGH(63) + +#define K_BCM1480_INT_BAD_ECC _BCM1480_INT_LOW(1) +#define K_BCM1480_INT_COR_ECC _BCM1480_INT_LOW(2) +#define K_BCM1480_INT_IO_BUS _BCM1480_INT_LOW(3) +#define K_BCM1480_INT_PERF_CNT _BCM1480_INT_LOW(4) +#define K_BCM1480_INT_SW_PERF_CNT _BCM1480_INT_LOW(5) +#define K_BCM1480_INT_TRACE_FREEZE _BCM1480_INT_LOW(6) +#define K_BCM1480_INT_SW_TRACE_FREEZE _BCM1480_INT_LOW(7) +#define K_BCM1480_INT_WATCHDOG_TIMER_0 _BCM1480_INT_LOW(8) +#define K_BCM1480_INT_WATCHDOG_TIMER_1 _BCM1480_INT_LOW(9) +#define K_BCM1480_INT_WATCHDOG_TIMER_2 _BCM1480_INT_LOW(10) +#define K_BCM1480_INT_WATCHDOG_TIMER_3 _BCM1480_INT_LOW(11) +#define K_BCM1480_INT_PCI_ERROR _BCM1480_INT_LOW(16) +#define K_BCM1480_INT_PCI_RESET _BCM1480_INT_LOW(17) +#define K_BCM1480_INT_NODE_CONTROLLER _BCM1480_INT_LOW(18) +#define K_BCM1480_INT_HOST_BRIDGE _BCM1480_INT_LOW(19) +#define K_BCM1480_INT_PORT_0_FATAL _BCM1480_INT_LOW(20) +#define K_BCM1480_INT_PORT_0_NONFATAL _BCM1480_INT_LOW(21) +#define K_BCM1480_INT_PORT_1_FATAL _BCM1480_INT_LOW(22) +#define K_BCM1480_INT_PORT_1_NONFATAL _BCM1480_INT_LOW(23) +#define K_BCM1480_INT_PORT_2_FATAL _BCM1480_INT_LOW(24) +#define K_BCM1480_INT_PORT_2_NONFATAL _BCM1480_INT_LOW(25) +#define K_BCM1480_INT_LDT_SMI _BCM1480_INT_LOW(32) +#define K_BCM1480_INT_LDT_NMI _BCM1480_INT_LOW(33) +#define K_BCM1480_INT_LDT_INIT _BCM1480_INT_LOW(34) +#define K_BCM1480_INT_LDT_STARTUP _BCM1480_INT_LOW(35) +#define K_BCM1480_INT_LDT_EXT _BCM1480_INT_LOW(36) +#define K_BCM1480_INT_SMB_0 _BCM1480_INT_LOW(40) +#define K_BCM1480_INT_SMB_1 _BCM1480_INT_LOW(41) +#define K_BCM1480_INT_PCMCIA _BCM1480_INT_LOW(42) +#define K_BCM1480_INT_UART_0 _BCM1480_INT_LOW(44) +#define K_BCM1480_INT_UART_1 _BCM1480_INT_LOW(45) +#define K_BCM1480_INT_UART_2 _BCM1480_INT_LOW(46) +#define K_BCM1480_INT_UART_3 _BCM1480_INT_LOW(47) +#define K_BCM1480_INT_GPIO_4 _BCM1480_INT_LOW(52) +#define K_BCM1480_INT_GPIO_5 _BCM1480_INT_LOW(53) +#define K_BCM1480_INT_GPIO_6 _BCM1480_INT_LOW(54) +#define K_BCM1480_INT_GPIO_7 _BCM1480_INT_LOW(55) +#define K_BCM1480_INT_GPIO_8 _BCM1480_INT_LOW(56) +#define K_BCM1480_INT_GPIO_9 _BCM1480_INT_LOW(57) +#define K_BCM1480_INT_GPIO_10 _BCM1480_INT_LOW(58) +#define K_BCM1480_INT_GPIO_11 _BCM1480_INT_LOW(59) +#define K_BCM1480_INT_GPIO_12 _BCM1480_INT_LOW(60) +#define K_BCM1480_INT_GPIO_13 _BCM1480_INT_LOW(61) +#define K_BCM1480_INT_GPIO_14 _BCM1480_INT_LOW(62) +#define K_BCM1480_INT_GPIO_15 _BCM1480_INT_LOW(63) + +/* +* Mask values for each interrupt +*/ + +#define _BCM1480_INT_MASK1 (n) _SB_MAKEMASK1(((n) & 0x3F)) +#define _BCM1480_INT_OFFSET (n) (((n) & 0x40) << 6) + +#define M_BCM1480_INT_CASCADE _BCM1480_INT_MASK1(_BCM1480_INT_HIGH(0)) + +#define M_BCM1480_INT_ADDR_TRAP _BCM1480_INT_MASK1(K_BCM1480_INT_ADDR_TRAP) +#define M_BCM1480_INT_GPIO_0 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_0) +#define M_BCM1480_INT_GPIO_1 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_1) +#define M_BCM1480_INT_GPIO_2 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_2) +#define M_BCM1480_INT_GPIO_3 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_3) +#define M_BCM1480_INT_PCI_INTA _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTA) +#define M_BCM1480_INT_PCI_INTB _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTB) +#define M_BCM1480_INT_PCI_INTC _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTC) +#define M_BCM1480_INT_PCI_INTD _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTD) +#define M_BCM1480_INT_CYCLE_CP0 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP0) +#define M_BCM1480_INT_CYCLE_CP1 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP1) +#define M_BCM1480_INT_CYCLE_CP2 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP2) +#define M_BCM1480_INT_CYCLE_CP3 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP3) +#define M_BCM1480_INT_TIMER_0 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_0) +#define M_BCM1480_INT_TIMER_1 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_1) +#define M_BCM1480_INT_TIMER_2 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_2) +#define M_BCM1480_INT_TIMER_3 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_3) +#define M_BCM1480_INT_DM_CH_0 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_0) +#define M_BCM1480_INT_DM_CH_1 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_1) +#define M_BCM1480_INT_DM_CH_2 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_2) +#define M_BCM1480_INT_DM_CH_3 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_3) +#define M_BCM1480_INT_MAC_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0) +#define M_BCM1480_INT_MAC_0_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0_CH1) +#define M_BCM1480_INT_MAC_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1) +#define M_BCM1480_INT_MAC_1_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1_CH1) +#define M_BCM1480_INT_MAC_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2) +#define M_BCM1480_INT_MAC_2_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2_CH1) +#define M_BCM1480_INT_MAC_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3) +#define M_BCM1480_INT_MAC_3_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3_CH1) +#define M_BCM1480_INT_PMI_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_LOW) +#define M_BCM1480_INT_PMI_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH) +#define M_BCM1480_INT_PMO_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW) +#define M_BCM1480_INT_PMO_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH) +#define M_BCM1480_INT_MBOX_0_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0) +#define M_BCM1480_INT_MBOX_0_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1) +#define M_BCM1480_INT_MBOX_0_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2) +#define M_BCM1480_INT_MBOX_0_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_3) +#define M_BCM1480_INT_MBOX_1_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_0) +#define M_BCM1480_INT_MBOX_1_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_1) +#define M_BCM1480_INT_MBOX_1_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_2) +#define M_BCM1480_INT_MBOX_1_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_3) +#define M_BCM1480_INT_BAD_ECC _BCM1480_INT_MASK1(K_BCM1480_INT_BAD_ECC) +#define M_BCM1480_INT_COR_ECC _BCM1480_INT_MASK1(K_BCM1480_INT_COR_ECC) +#define M_BCM1480_INT_IO_BUS _BCM1480_INT_MASK1(K_BCM1480_INT_IO_BUS) +#define M_BCM1480_INT_PERF_CNT _BCM1480_INT_MASK1(K_BCM1480_INT_PERF_CNT) +#define M_BCM1480_INT_SW_PERF_CNT _BCM1480_INT_MASK1(K_BCM1480_INT_SW_PERF_CNT) +#define M_BCM1480_INT_TRACE_FREEZE _BCM1480_INT_MASK1(K_BCM1480_INT_TRACE_FREEZE) +#define M_BCM1480_INT_SW_TRACE_FREEZE _BCM1480_INT_MASK1(K_BCM1480_INT_SW_TRACE_FREEZE) +#define M_BCM1480_INT_WATCHDOG_TIMER_0 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_0) +#define M_BCM1480_INT_WATCHDOG_TIMER_1 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_1) +#define M_BCM1480_INT_WATCHDOG_TIMER_2 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_2) +#define M_BCM1480_INT_WATCHDOG_TIMER_3 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_3) +#define M_BCM1480_INT_PCI_ERROR _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_ERROR) +#define M_BCM1480_INT_PCI_RESET _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_RESET) +#define M_BCM1480_INT_NODE_CONTROLLER _BCM1480_INT_MASK1(K_BCM1480_INT_NODE_CONTROLLER) +#define M_BCM1480_INT_HOST_BRIDGE _BCM1480_INT_MASK1(K_BCM1480_INT_HOST_BRIDGE) +#define M_BCM1480_INT_PORT_0_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_FATAL) +#define M_BCM1480_INT_PORT_0_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_NONFATAL) +#define M_BCM1480_INT_PORT_1_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_FATAL) +#define M_BCM1480_INT_PORT_1_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_NONFATAL) +#define M_BCM1480_INT_PORT_2_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_FATAL) +#define M_BCM1480_INT_PORT_2_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_NONFATAL) +#define M_BCM1480_INT_LDT_SMI _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_SMI) +#define M_BCM1480_INT_LDT_NMI _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_NMI) +#define M_BCM1480_INT_LDT_INIT _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_INIT) +#define M_BCM1480_INT_LDT_STARTUP _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_STARTUP) +#define M_BCM1480_INT_LDT_EXT _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_EXT) +#define M_BCM1480_INT_SMB_0 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_0) +#define M_BCM1480_INT_SMB_1 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_1) +#define M_BCM1480_INT_PCMCIA _BCM1480_INT_MASK1(K_BCM1480_INT_PCMCIA) +#define M_BCM1480_INT_UART_0 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_0) +#define M_BCM1480_INT_UART_1 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_1) +#define M_BCM1480_INT_UART_2 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_2) +#define M_BCM1480_INT_UART_3 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_3) +#define M_BCM1480_INT_GPIO_4 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_4) +#define M_BCM1480_INT_GPIO_5 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_5) +#define M_BCM1480_INT_GPIO_6 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_6) +#define M_BCM1480_INT_GPIO_7 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_7) +#define M_BCM1480_INT_GPIO_8 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_8) +#define M_BCM1480_INT_GPIO_9 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_9) +#define M_BCM1480_INT_GPIO_10 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_10) +#define M_BCM1480_INT_GPIO_11 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_11) +#define M_BCM1480_INT_GPIO_12 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_12) +#define M_BCM1480_INT_GPIO_13 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_13) +#define M_BCM1480_INT_GPIO_14 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_14) +#define M_BCM1480_INT_GPIO_15 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_15) + +/* +* Interrupt mappings (Table 18) +*/ + +#define K_BCM1480_INT_MAP_I0 0/* interrupt pins on processor */ +#define K_BCM1480_INT_MAP_I1 1 +#define K_BCM1480_INT_MAP_I2 2 +#define K_BCM1480_INT_MAP_I3 3 +#define K_BCM1480_INT_MAP_I4 4 +#define K_BCM1480_INT_MAP_I5 5 +#define K_BCM1480_INT_MAP_NMI 6/* nonmaskable */ +#define K_BCM1480_INT_MAP_DINT 7/* debug interrupt */ + +/* +* Interrupt LDT Set Register (Table 19) +*/ + +#define S_BCM1480_INT_HT_INTMSG 0 +#define M_BCM1480_INT_HT_INTMSG _SB_MAKEMASK(3,S_BCM1480_INT_HT_INTMSG) +#define V_BCM1480_INT_HT_INTMSG (x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_INTMSG) +#define G_BCM1480_INT_HT_INTMSG (x) _SB_GETVALUE(x,S_BCM1480_INT_HT_INTMSG,M_BCM1480_INT_HT_INTMSG) + +#define K_BCM1480_INT_HT_INTMSG_FIXED 0 +#define K_BCM1480_INT_HT_INTMSG_ARBITRATED 1 +#define K_BCM1480_INT_HT_INTMSG_SMI 2 +#define K_BCM1480_INT_HT_INTMSG_NMI 3 +#define K_BCM1480_INT_HT_INTMSG_INIT 4 +#define K_BCM1480_INT_HT_INTMSG_STARTUP 5 +#define K_BCM1480_INT_HT_INTMSG_EXTINT 6 +#define K_BCM1480_INT_HT_INTMSG_RESERVED 7 + +#define M_BCM1480_INT_HT_TRIGGERMODE _SB_MAKEMASK1(3) +#define V_BCM1480_INT_HT_EDGETRIGGER 0 +#define V_BCM1480_INT_HT_LEVELTRIGGER M_BCM1480_INT_HT_TRIGGERMODE + +#define M_BCM1480_INT_HT_DESTMODE _SB_MAKEMASK1(4) +#define V_BCM1480_INT_HT_PHYSICALDEST 0 +#define V_BCM1480_INT_HT_LOGICALDEST M_BCM1480_INT_HT_DESTMODE + +#define S_BCM1480_INT_HT_INTDEST 5 +#define M_BCM1480_INT_HT_INTDEST _SB_MAKEMASK(8,S_BCM1480_INT_HT_INTDEST) +#define V_BCM1480_INT_HT_INTDEST (x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_INTDEST) +#define G_BCM1480_INT_HT_INTDEST (x) _SB_GETVALUE(x,S_BCM1480_INT_HT_INTDEST,M_BCM1480_INT_HT_INTDEST) + +#define S_BCM1480_INT_HT_VECTOR 13 +#define M_BCM1480_INT_HT_VECTOR _SB_MAKEMASK(8,S_BCM1480_INT_HT_VECTOR) +#define V_BCM1480_INT_HT_VECTOR (x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_VECTOR) +#define G_BCM1480_INT_HT_VECTOR (x) _SB_GETVALUE(x,S_BCM1480_INT_HT_VECTOR,M_BCM1480_INT_HT_VECTOR) + +/* +* Vector prefix (Table 4-7) +*/ + +#define M_BCM1480_HTVECT_RAISE_INTLDT_HIGH 0x00 +#define M_BCM1480_HTVECT_RAISE_MBOX_0 0x40 +#define M_BCM1480_HTVECT_RAISE_INTLDT_LO 0x80 +#define M_BCM1480_HTVECT_RAISE_MBOX_1 0xC0 + +#endif /* _BCM1480_INT_H */
include/asm-mips/sibyte/bcm1480_l2c.h new file +176 -0
176 lines not on this page · raw message
include/asm-mips/sibyte/bcm1480_mc.h new file +962 -0
962 lines not on this page · raw message
include/asm-mips/sibyte/bcm1480_regs.h new file +869 -0
869 lines not on this page · raw message
include/asm-mips/sibyte/bcm1480_scd.h new file +436 -0
436 lines not on this page · raw message
include/asm-mips/sibyte/sb1250_defs.h +26 -7
@@ -97,13 +97,17 @@* ordering, so be careful when adding support for new minor revs. ********************************************************************* */ -#define SIBYTE_HDR_FMASK_1250_ALL 0x00000ff -#define SIBYTE_HDR_FMASK_1250_PASS1 0x0000001 -#define SIBYTE_HDR_FMASK_1250_PASS2 0x0000002 -#define SIBYTE_HDR_FMASK_1250_PASS3 0x0000004 - -#define SIBYTE_HDR_FMASK_112x_ALL 0x0000f00 -#define SIBYTE_HDR_FMASK_112x_PASS1 0x0000100 +#define SIBYTE_HDR_FMASK_1250_ALL 0x000000ff +#define SIBYTE_HDR_FMASK_1250_PASS1 0x00000001 +#define SIBYTE_HDR_FMASK_1250_PASS2 0x00000002 +#define SIBYTE_HDR_FMASK_1250_PASS3 0x00000004 + +#define SIBYTE_HDR_FMASK_112x_ALL 0x00000f00 +#define SIBYTE_HDR_FMASK_112x_PASS1 0x00000100 + +#define SIBYTE_HDR_FMASK_1480_ALL 0x0000f000 +#define SIBYTE_HDR_FMASK_1480_PASS1 0x00001000 +#define SIBYTE_HDR_FMASK_1480_PASS2 0x00002000/* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */ #define SIBYTE_HDR_FMASK (chip, pass) \
@@ -111,8 +115,17 @@#define SIBYTE_HDR_FMASK_ALLREVS (chip) \ (SIBYTE_HDR_FMASK_ ## chip ## _ALL) +/* Default constant value for all chips, all revisions */ #define SIBYTE_HDR_FMASK_ALL \ + (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL \ + | SIBYTE_HDR_FMASK_1480_ALL) + +/* This one is used for the "original" BCM1250/BCM112x chips. We use this +to weed out constants and macros that do not exist on later chips like +the BCM1480 */ +#define SIBYTE_HDR_FMASK_1250_112x_ALL \ (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL) +#define SIBYTE_HDR_FMASK_1250_112x SIBYTE_HDR_FMASK_1250_112x_ALL#ifndef SIBYTE_HDR_FEATURES #define SIBYTE_HDR_FEATURES SIBYTE_HDR_FMASK_ALL
@@ -133,6 +146,12 @@#define SIBYTE_HDR_FEATURE_CHIP (chip) \ (!! (SIBYTE_HDR_FMASK_ALLREVS(chip) & SIBYTE_HDR_FEATURES)) +/* True for all versions of the BCM1250 and BCM1125, but not true for +anything else */ +#define SIBYTE_HDR_FEATURE_1250_112x \ + (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x)) +/* (!! (SIBYTE_HDR_FEATURES & SIBYHTE_HDR_FMASK_1250_112x)) */ +/* True if header features enabled for that rev or later, inclusive. */ #define SIBYTE_HDR_FEATURE (chip, pass) \ (!! ((SIBYTE_HDR_FMASK(chip, pass) \
include/asm-mips/sibyte/sb1250_dma.h +33 -32
194 lines not on this page · raw message
include/asm-mips/sibyte/sb1250_genbus.h +212 -13
225 lines not on this page · raw message
include/asm-mips/sibyte/sb1250_scd.h +82 -18
100 lines not on this page · raw message
include/asm-mips/sibyte/sb1250_smbus.h +44 -9
53 lines not on this page · raw message
The rest of this diff is not shown. View the raw message.
Part of the diff is not shown here. View the raw message.
PATCH 3/12 sibyte-header-cleanup
In reply to Andrew IsaacsonUpdate sibyte headers to match Broadcom internal copies:
- comment cleanup and updates
- fix LittleSur part number to match the board silkscreen
Signed-off-by Andy Isaacson <[email protected]>
include/asm-mips/sibyte/sb1250_defs.h | 2 -- include/asm-mips/sibyte/sb1250_dma.h | 5 ++--- include/asm-mips/sibyte/sb1250_genbus.h | 5 ++--- include/asm-mips/sibyte/sb1250_int.h | 2 -- include/asm-mips/sibyte/sb1250_l2c.h | 2 -- include/asm-mips/sibyte/sb1250_ldt.h | 2 -- include/asm-mips/sibyte/sb1250_mac.h | 2 -- include/asm-mips/sibyte/sb1250_mc.h | 2 -- include/asm-mips/sibyte/sb1250_regs.h | 2 -- include/asm-mips/sibyte/sb1250_scd.h | 2 -- include/asm-mips/sibyte/sb1250_smbus.h | 5 ++--- include/asm-mips/sibyte/sb1250_syncser.h | 2 -- include/asm-mips/sibyte/sb1250_uart.h | 2 -- include/asm-mips/sibyte/swarm.h | 2 +- 14 files changed, 7 insertions(+), 30 deletions(-)
include/asm-mips/sibyte/sb1250_defs.h +0 -2
@@ -8,8 +8,6 @@* * SB1250 specification level: User's manual 1/02/02 * -* Author: Mitch Lichtenberg -* ********************************************************************* * * Copyright 2000,2001,2002,2003
include/asm-mips/sibyte/sb1250_dma.h +2 -3
@@ -7,9 +7,8 @@* programming the SB1250's DMA controllers, both the data mover * and the Ethernet DMA. * -* SB1250 specification level: User's manual 1/02/02 -* -* Author: Mitch Lichtenberg +* SB1250 specification level: User's manual 10/21/02 +* BCM1280 specification level: User's manual 11/24/03 * ********************************************************************* *
include/asm-mips/sibyte/sb1250_genbus.h +2 -3
@@ -6,9 +6,8 @@* This module contains constants and macros useful for * manipulating the SB1250's Generic Bus interface * -* SB1250 specification level: User's manual 1/02/02 -* -* Author: Mitch Lichtenberg +* SB1250 specification level: User's manual 10/21/02 +* BCM1280 specification level: User's Manual 11/14/03 * ********************************************************************* *
include/asm-mips/sibyte/sb1250_int.h +0 -2
@@ -8,8 +8,6 @@* * SB1250 specification level: User's manual 1/02/02 * -* Author: Mitch Lichtenberg -* ********************************************************************* * * Copyright 2000,2001,2002,2003
include/asm-mips/sibyte/sb1250_l2c.h +0 -2
@@ -8,8 +8,6 @@* * SB1250 specification level: User's manual 1/02/02 * -* Author: Mitch Lichtenberg -* ********************************************************************* * * Copyright 2000,2001,2002,2003
include/asm-mips/sibyte/sb1250_ldt.h +0 -2
@@ -8,8 +8,6 @@* * SB1250 specification level: User's manual 1/02/02 * -* Author: Mitch Lichtenberg -* ********************************************************************* * * Copyright 2000,2001,2002,2003
include/asm-mips/sibyte/sb1250_mac.h +0 -2
@@ -8,8 +8,6 @@* * SB1250 specification level: User's manual 1/02/02 * -* Author: Mitch Lichtenberg -* ********************************************************************* * * Copyright 2000,2001,2002,2003
include/asm-mips/sibyte/sb1250_mc.h +0 -2
@@ -8,8 +8,6 @@* * SB1250 specification level: User's manual 1/02/02 * -* Author: Mitch Lichtenberg -* ********************************************************************* * * Copyright 2000,2001,2002,2003
include/asm-mips/sibyte/sb1250_regs.h +0 -2
@@ -8,8 +8,6 @@* * SB1250 specification level: 01/02/2002 * -* Author: Mitch Lichtenberg -* ********************************************************************* * * Copyright 2000,2001,2002,2003
include/asm-mips/sibyte/sb1250_scd.h +0 -2
@@ -8,8 +8,6 @@* * SB1250 specification level: User's manual 1/02/02 * -* Author: Mitch Lichtenberg -* ********************************************************************* * * Copyright 2000,2001,2002,2003
include/asm-mips/sibyte/sb1250_smbus.h +2 -3
@@ -6,9 +6,8 @@* This module contains constants and macros useful for * manipulating the SB1250's SMbus devices. * -* SB1250 specification level: 01/02/2002 -* -* Author: Mitch Lichtenberg +* SB1250 specification level: 10/21/02 +* BCM1280 specification level: 11/24/03 * ********************************************************************* *
include/asm-mips/sibyte/sb1250_syncser.h +0 -2
@@ -8,8 +8,6 @@* * SB1250 specification level: User's manual 1/02/02 * -* Author: Mitch Lichtenberg -* ********************************************************************* * * Copyright 2000,2001,2002,2003
include/asm-mips/sibyte/sb1250_uart.h +0 -2
@@ -8,8 +8,6 @@* * SB1250 specification level: User's manual 1/02/02 * -* Author: Mitch Lichtenberg -* ********************************************************************* * * Copyright 2000,2001,2002,2003
include/asm-mips/sibyte/swarm.h +1 -1
@@ -34,7 +34,7 @@#define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200"#endif #ifdef CONFIG_SIBYTE_LITTLESUR -#define SIBYTE_BOARD_NAME "BCM1250C2 (LittleSur)" +#define SIBYTE_BOARD_NAME "BCM91250C2 (LittleSur)"#define SIBYTE_HAVE_PCMCIA 0#define SIBYTE_HAVE_IDE 1#define SIBYTE_DEFAULT_CONSOLE "cfe0"
PATCH 4/12 sb1a-support
In reply to Andrew IsaacsonAdd support for SB-1A CPU.
Signed-off-by Andy Isaacson <[email protected]>
arch/mips/kernel/cpu-probe.c | 3 +++ arch/mips/kernel/proc.c | 1 + arch/mips/mm/tlbex.c | 1 + include/asm-mips/addrspace.h | 2 +- include/asm-mips/cpu.h | 4 +++- 5 files changed, 9 insertions(+), 2 deletions(-)
arch/mips/mm/tlbex.c +1 -0
@@ -854,6 +854,7 @@case CPU_R12000 :case CPU_4KC :case CPU_SB1 : +case CPU_SB1A :case CPU_4KSC :case CPU_20KC :case CPU_25KF :
arch/mips/kernel/cpu-probe.c +3 -0
@@ -629,6 +629,9 @@ c->options &= ~(MIPS_CPU_FPU |MIPS_CPU_32FPR );#endif break ; +case PRID_IMP_SB1A : + c->cputype =CPU_SB1A ; +break ; } }
arch/mips/kernel/proc.c +1 -0
@@ -56,6 +56,7 @@ [CPU_5KC] = "MIPS 5Kc", [CPU_R4310] = "R4310", [CPU_SB1] = "SiByte SB1", + [CPU_SB1A] = "SiByte SB1A", [CPU_TX3912] = "TX3912", [CPU_TX3922] = "TX3922", [CPU_TX3927] = "TX3927",
include/asm-mips/cpu.h +3 -1
@@ -93,6 +93,7 @@*/ #define PRID_IMP_SB1 0x0100 +#define PRID_IMP_SB1A 0x1100/* * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
@@ -194,7 +195,8 @@#define CPU_AU1200 59#define CPU_34K 60#define CPU_PR4450 61 -#define CPU_LAST 61 +#define CPU_SB1A 62 +#define CPU_LAST 62/* * ISA Level encodings
include/asm-mips/addrspace.h +1 -1
@@ -162,7 +162,7 @@#define TO_PHYS_MASK _LLCONST_(0x000000ffffffffff)/* 2^^40 - 1 */ #endif -#if defined(CONFIG_CPU_SB1 ) +#if defined(CONFIG_CPU_SB1 ) || defined(CONFIG_CPU_SB1A )#define KUSIZE _LLCONST_(0x0000100000000000)/* 2^^44 */ #define KUSIZE_64 _LLCONST_(0x0000100000000000)/* 2^^44 */ #define K0SIZE _LLCONST_(0x0000100000000000)/* 2^^44 */
PATCH 5/12 1480-support
In reply to Andrew IsaacsonAdd support for BCM1480 family of chips.
- Kconfig and Makefile changes
- arch/mips/sibyte/bcm1480/
- changes to sibyte common code to support 1480
Signed-off-by Andy Isaacson <[email protected]>
arch/mips/Kconfig | 2 arch/mips/Makefile | 14 arch/mips/sibyte/Kconfig | 10 arch/mips/sibyte/bcm1480/Makefile | 5 arch/mips/sibyte/bcm1480/irq.c | 476 +++++++++++++++++++++++++++++++++ arch/mips/sibyte/bcm1480/irq_handler.S | 165 +++++++++++ arch/mips/sibyte/bcm1480/setup.c | 136 +++++++++ arch/mips/sibyte/bcm1480/smp.c | 110 +++++++ arch/mips/sibyte/bcm1480/time.c | 138 +++++++++ arch/mips/sibyte/cfe/smp.c | 14 arch/mips/sibyte/swarm/setup.c | 28 + drivers/char/sb1250_duart.c | 90 ++++-- drivers/net/sb1250-mac.c | 109 ++++--- 13 files changed, 1230 insertions(+), 67 deletions(-)
arch/mips/Makefile +12 -2
@@ -647,10 +647,20 @@ # removed (as happens, even if they have __initcall/module_init) # core-$(CONFIG_SIBYTE_BCM112X) += arch/mips/sibyte/sb1250/ -cflags-$(CONFIG_SIBYTE_BCM112X) += -Iinclude/asm-mips/mach-sibyte +cflags-$(CONFIG_SIBYTE_BCM112X) += -Iinclude/asm-mips/mach-sibyte \ + -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL core-$(CONFIG_SIBYTE_SB1250) += arch/mips/sibyte/sb1250/ -cflags-$(CONFIG_SIBYTE_SB1250) += -Iinclude/asm-mips/mach-sibyte +cflags-$(CONFIG_SIBYTE_SB1250) += -Iinclude/asm-mips/mach-sibyte \ + -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL + +core-$(CONFIG_SIBYTE_BCM1x55) += arch/mips/sibyte/bcm1480/ +cflags-$(CONFIG_SIBYTE_BCM1x55) += -Iinclude/asm-mips/mach-sibyte \ + -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL + +core-$(CONFIG_SIBYTE_BCM1x80) += arch/mips/sibyte/bcm1480/ +cflags-$(CONFIG_SIBYTE_BCM1x80) += -Iinclude/asm-mips/mach-sibyte \ + -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL # # Sibyte BCM91120x (Carmel) board
arch/mips/sibyte/bcm1480/Makefile new file +5 -0
@@ -0,0 +1,5 @@ +obj-y := setup.o irq.o irq_handler.o time.o + +obj-$(CONFIG_SMP) += smp.o + +EXTRA_AFLAGS := $(CFLAGS)
arch/mips/sibyte/bcm1480/irq.c new file +476 -0
476 lines not on this page · raw message
arch/mips/sibyte/bcm1480/irq_handler.S new file +165 -0
165 lines not on this page · raw message
arch/mips/sibyte/bcm1480/setup.c new file +136 -0
136 lines not on this page · raw message
arch/mips/sibyte/bcm1480/smp.c new file +110 -0
110 lines not on this page · raw message
arch/mips/sibyte/bcm1480/time.c new file +138 -0
138 lines not on this page · raw message
arch/mips/sibyte/cfe/smp.c +14 -0
@@ -70,8 +70,15 @@*/ void prom_init_secondary (void ) { +#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) +extern void bcm1480_smp_init (void ); +bcm1480_smp_init (); +#elif defined(CONFIG_SIBYTE_SB1250 )extern void sb1250_smp_init (void );sb1250_smp_init (); +#else +#error invalid SMP configuration +#endif }/*
@@ -80,8 +87,15 @@*/ void prom_smp_finish (void ) { +#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) +extern void bcm1480_smp_finish (void ); +bcm1480_smp_finish (); +#elif defined(CONFIG_SIBYTE_SB1250 )extern void sb1250_smp_finish (void );sb1250_smp_finish (); +#else +#error invalid SMP configuration +#endif }/*
arch/mips/sibyte/swarm/setup.c +26 -2
@@ -1,5 +1,5 @@/* -* Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation +* Copyright (C) 2000, 2001, 2002, 2003, 2004 Broadcom Corporation * Copyright (C) 2004 by Ralf Baechle ([email protected]) * * This program is free software; you can redistribute it and/or
@@ -39,11 +39,23 @@#include <asm/time.h> #include <asm/traps.h> #include <asm/sibyte/sb1250.h> +#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) +#include <asm/sibyte/bcm1480_regs.h> +#elif defined(CONFIG_SIBYTE_SB1250 ) || defined(CONFIG_SIBYTE_BCM112X )#include <asm/sibyte/sb1250_regs.h> +#else +#error invalid SiByte board configuation +#endif #include <asm/sibyte/sb1250_genbus.h> #include <asm/sibyte/board.h> +#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) +extern void bcm1480_setup (void ); +#elif defined(CONFIG_SIBYTE_SB1250 ) || defined(CONFIG_SIBYTE_BCM112X )extern void sb1250_setup (void ); +#else +#error invalid SiByte board configuation +#endif extern int xicor_probe (void );extern int xicor_set_time (unsigned long );
@@ -66,7 +78,13 @@*/ /* We only need to setup the generic timer */ -sb1250_time_init (); +#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) +bcm1480_time_init (); +#elif defined(CONFIG_SIBYTE_SB1250 ) || defined(CONFIG_SIBYTE_BCM112X ) +sb1250_time_init (); +#else +#error invalid SiByte board configuation +#endif }int swarm_be_handler (struct pt_regs *regs,int is_fixup)
@@ -81,7 +99,13 @@void __init plat_setup (void ) { +#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) +bcm1480_setup (); +#elif defined(CONFIG_SIBYTE_SB1250 ) || defined(CONFIG_SIBYTE_BCM112X )sb1250_setup (); +#else +#error invalid SiByte board configuation +#endif panic_timeout =5 ;/* For debug. */
drivers/char/sb1250_duart.c +67 -23
160 lines not on this page · raw message
drivers/net/sb1250-mac.c +70 -39
204 lines not on this page · raw message
arch/mips/Kconfig +1 -1
@@ -1430,7 +1430,7 @@ config SMP bool "Multi-Processing support" - depends on CPU_RM9000 || (SIBYTE_SB1250 && !SIBYTE_STANDALONE) || SGI_IP27 || MIPS_MT_SMP + depends on CPU_RM9000 || ((SIBYTE_BCM1x80 || SIBYTE_BCM1x55 || SIBYTE_SB1250) && !SIBYTE_STANDALONE) || SGI_IP27 || MIPS_MT_SMP ---help--- This enables support for systems with more than one CPU. If you have a system with only one CPU, like most personal computers, say N. If
arch/mips/sibyte/Kconfig +10 -0
@@ -26,6 +26,16 @@ bool select SIBYTE_SB1xxx_SOC +config SIBYTE_BCM1x80 + bool + select HW_HAS_PCI + select SIBYTE_SB1xxx_SOC + +config SIBYTE_BCM1x55 + bool + select HW_HAS_PCI + select SIBYTE_SB1xxx_SOC + config SIBYTE_SB1xxx_SOC bool depends on EXPERIMENTAL
PATCH 6/12 bigsur-support
In reply to Andrew IsaacsonSupport for BigSur board.
Signed-off-by Andy Isaacson <[email protected]>
arch/mips/Kconfig | 9 arch/mips/Makefile | 3 arch/mips/configs/bigsur_defconfig | 877 +++++++++++++++++++++++++++++++++++++ include/asm-mips/sibyte/bigsur.h | 49 ++ include/asm-mips/sibyte/board.h | 4 5 files changed, 942 insertions(+)
arch/mips/configs/bigsur_defconfig new file +877 -0
@@ -0,0 +1,877 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.14-rc2 +# Wed Oct 19 23:36:33 2005 +# +CONFIG_MIPS=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_CLEAN_COMPILE=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +# CONFIG_AUDIT is not set +# CONFIG_HOTPLUG is not set +CONFIG_KOBJECT_UEVENT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +# CONFIG_CPUSETS is not set +CONFIG_INITRAMFS_SOURCE="" +CONFIG_EMBEDDED=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SHMEM=y +CONFIG_CC_ALIGN_FUNCTIONS=0 +CONFIG_CC_ALIGN_LABELS=0 +CONFIG_CC_ALIGN_LOOPS=0 +CONFIG_CC_ALIGN_JUMPS=0 +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_KMOD=y +CONFIG_STOP_MACHINE=y + +# +# Machine selection +# +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_3 is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +CONFIG_SIBYTE_BIGSUR=y +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +CONFIG_SIBYTE_BCM1x80=y +CONFIG_SIBYTE_SB1xxx_SOC=y +# CONFIG_CPU_SB1_PASS_1 is not set +# CONFIG_CPU_SB1_PASS_2_1250 is not set +# CONFIG_CPU_SB1_PASS_2_2 is not set +# CONFIG_CPU_SB1_PASS_4 is not set +# CONFIG_CPU_SB1_PASS_2_112x is not set +# CONFIG_CPU_SB1_PASS_3 is not set +# CONFIG_SIMULATION is not set +CONFIG_SIBYTE_CFE=y +# CONFIG_SIBYTE_CFE_CONSOLE is not set +# CONFIG_SIBYTE_BUS_WATCHER is not set +# CONFIG_SIBYTE_SB1250_PROF is not set +# CONFIG_SIBYTE_TBPROF is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_DMA_COHERENT=y +CONFIG_CPU_BIG_ENDIAN=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_BOOT_ELF32=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +CONFIG_CPU_SB1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +# CONFIG_32BIT is not set +CONFIG_64BIT=y +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_SIBYTE_DMA_PAGEOPS is not set +# CONFIG_MIPS_MT is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_LLDSCD=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SMP=y +CONFIG_NR_CPUS=4 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +# CONFIG_PREEMPT_BKL is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +CONFIG_PCI_LEGACY_PROC=y +CONFIG_PCI_DEBUG=y +CONFIG_MMU=y + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# PCI Hotplug Support +# +# CONFIG_HOTPLUG_PCI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_BUILD_ELF64=y +CONFIG_MIPS32_COMPAT=y +CONFIG_COMPAT=y +CONFIG_MIPS32_O32=y +# CONFIG_MIPS32_N32 is not set +CONFIG_BINFMT_ELF32=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_IEEE80211 is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +CONFIG_BLK_DEV_NBD=m +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_RAM is not set +CONFIG_BLK_DEV_RAM_COUNT=16 +# CONFIG_CDROM_PKTCDVD is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_ATA_OVER_ETH is not set + +# +# ATA/ATAPI/MFM/RLL support +# +CONFIG_IDE=y +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_IDEDISK=y +# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_BLK_DEV_IDECD=y +CONFIG_BLK_DEV_IDETAPE=y +CONFIG_BLK_DEV_IDEFLOPPY=y +# CONFIG_IDE_TASK_IOCTL is not set + +# +# IDE chipset support/bugfixes +# +CONFIG_IDE_GENERIC=y +# CONFIG_BLK_DEV_IDEPCI is not set +# CONFIG_BLK_DEV_IDE_SWARM is not set +# CONFIG_IDE_ARM is not set +# CONFIG_BLK_DEV_IDEDMA is not set +# CONFIG_IDEDMA_AUTO is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set + +# +# PHY device support +# +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_NET_VENDOR_3COM is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_NET_PCI is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +CONFIG_NET_SB1250_MAC=y +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set + +# +# Ethernet (10000 Mbit) +# +# CONFIG_CHELSIO_T1 is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set + +# +# Token Ring devices +# +# CONFIG_TR is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +# CONFIG_INPUT is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_ROCKETPORT is not set +# CONFIG_CYCLADES is not set +# CONFIG_DIGIEPCA is not set +# CONFIG_MOXA_SMARTIO is not set +# CONFIG_ISI is not set +# CONFIG_SYNCLINKMP is not set +# CONFIG_N_HDLC is not set +# CONFIG_SPECIALIX is not set +# CONFIG_SX is not set +# CONFIG_STALDRV is not set +CONFIG_SIBYTE_SB1250_DUART=y +CONFIG_SIBYTE_SB1250_DUART_CONSOLE=y + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_RTC is not set +CONFIG_GEN_RTC=y +# CONFIG_GEN_RTC_X is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set +CONFIG_I2C_ALGO_SIBYTE=y + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_I810 is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_PROSAVAGE is not set +# CONFIG_I2C_SAVAGE4 is not set +CONFIG_I2C_SIBYTE=y +# CONFIG_SCx200_ACB is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_VOODOO3 is not set +# CONFIG_I2C_PCA_ISA is not set + +# +# Miscellaneous I2C Chip support +# +CONFIG_SENSORS_DS1337=y +CONFIG_SENSORS_DS1374=y +CONFIG_SENSORS_EEPROM=y +CONFIG_SENSORS_PCF8574=y +CONFIG_SENSORS_PCA9539=y +CONFIG_SENSORS_PCF8591=y +CONFIG_SENSORS_RTC8564=y +CONFIG_SENSORS_MAX6875=y +CONFIG_I2C_DEBUG_CORE=y +CONFIG_I2C_DEBUG_ALGO=y +CONFIG_I2C_DEBUG_BUS=y +CONFIG_I2C_DEBUG_CHIP=y + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set + +# +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# +# Misc devices +# + +# +# Multimedia Capabilities Port drivers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# Graphics support +# +# CONFIG_FB is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB is not set + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set + +# +# MMC/SD Card support +# +# CONFIG_MMC is not set + +# +# InfiniBand support +# +# CONFIG_INFINIBAND is not set + +# +# SN Devices +# + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_SYSFS=y +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_RELAYFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +# CONFIG_NLS is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_KERNEL=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_FS is not set +CONFIG_CROSSCOMPILE=y +CONFIG_CMDLINE="" +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_KGDB is not set +# CONFIG_SB1XXX_CORELIS is not set +# CONFIG_RUNTIME_DEBUG is not set + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_KEYS_DEBUG_PROC_KEYS=y +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_SERPENT=y +CONFIG_CRYPTO_AES=m +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_TEA=m +# CONFIG_CRYPTO_ARC4 is not set +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_MICHAEL_MIC=y +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Hardware crypto devices +# + +# +# Library routines +# +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y
arch/mips/Makefile +3 -0
@@ -668,6 +668,7 @@ # Sibyte BCM91125C (CRhone) board # Sibyte BCM91125E (Rhone) board # Sibyte SWARM board +# Sibyte BCM91x80 (BigSur) board # libs-$(CONFIG_SIBYTE_CARMEL) += arch/mips/sibyte/swarm/ load-$(CONFIG_SIBYTE_CARMEL) := 0xffffffff80100000
@@ -681,6 +682,8 @@ load-$(CONFIG_SIBYTE_SENTOSA) := 0xffffffff80100000 libs-$(CONFIG_SIBYTE_SWARM) += arch/mips/sibyte/swarm/ load-$(CONFIG_SIBYTE_SWARM) := 0xffffffff80100000 +libs-$(CONFIG_SIBYTE_BIGSUR) += arch/mips/sibyte/swarm/ +load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000 # # SNI RM200 PCI
arch/mips/Kconfig +9 -0
@@ -544,6 +544,15 @@ help If you want this kernel to run on SGI O2 workstation, say Y here. +config SIBYTE_BIGSUR + bool "Support for Sibyte BigSur" + select BOOT_ELF32 + select DMA_COHERENT + select SIBYTE_BCM1x80 + select SWAP_IO_SPACE + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_LITTLE_ENDIAN + config SIBYTE_SWARM bool "Support for Sibyte BCM91250A-SWARM" select BOOT_ELF32
include/asm-mips/sibyte/board.h +4 -0
@@ -35,6 +35,10 @@#include <asm/sibyte/carmel.h> #endif +#ifdef CONFIG_SIBYTE_BIGSUR +#include <asm/sibyte/bigsur.h> +#endif +#ifdef __ASSEMBLY__#ifdef LEDS_PHYS
include/asm-mips/sibyte/bigsur.h new file +49 -0
49 lines not on this page · raw message
PATCH 7/12 sb1-cache-exc-handling
In reply to Andrew IsaacsonExpand SB1 cache error handling by adding SB1_CEX_ALWAYS_FATAL and SB1_CEX_STALL, allowing configurable behavior on cache errors.
Signed-off-by Andy Isaacson <[email protected]>
arch/mips/mm/cerr-sb1.c | 54 ++++++++++++++++++++++++++++++++++++++++------- arch/mips/mm/cex-sb1.S | 5 ++++ arch/mips/sibyte/Kconfig | 8 ++++++ 3 files changed, 59 insertions(+), 8 deletions(-)
arch/mips/mm/cerr-sb1.c +46 -8
@@ -19,13 +19,19 @@#include <linux/sched.h> #include <asm/mipsregs.h> #include <asm/sibyte/sb1250.h> +#include <asm/sibyte/sb1250_regs.h> -#ifndef CONFIG_SIBYTE_BUS_WATCHER +#if !defined(CONFIG_SIBYTE_BUS_WATCHER ) || defined(CONFIG_SIBYTE_BW_TRACE )#include <asm/io.h> -#include <asm/sibyte/sb1250_regs.h> #include <asm/sibyte/sb1250_scd.h> #endif +/* +* We'd like to dump the L2_ECC_TAG register on errors, but errata make +* that unsafe... So for now we don't. (BCM1250/BCM112x erratum SOC-48.) +*/ +#undef DUMP_L2_ECC_TAG_ON_ERROR +/* SB1 definitions */ /* XXX should come from config1 XXX */
@@ -139,12 +145,18 @@static void check_bus_watcher (void ) {uint32_t status, l2_err, memio_err; +#ifdef DUMP_L2_ECC_TAG_ON_ERROR +uint64_t l2_tag; +#endif /* Destructive read, clears register and interrupt */ status =csr_in32 (IOADDR (A_SCD_BUS_ERR_STATUS ));/* Bit 31 is always on, but there's no #define for that */ if (status & ~(1UL <<31 )) { l2_err =csr_in32 (IOADDR (A_BUS_L2_ERRORS )); +#ifdef DUMP_L2_ECC_TAG_ON_ERROR + l2_tag =in64 (IO_SPACE_BASE |A_L2_ECC_TAG ); +#endif memio_err =csr_in32 (IOADDR (A_BUS_MEM_IO_ERRORS ));prom_printf ("Bus watcher error counters: %08x %08x\n" , l2_err, memio_err);prom_printf ("\nLast recorded signature:\n" );
@@ -153,6 +165,9 @@ (int )(G_SCD_BERR_TID (status) >>6 ), (int )G_SCD_BERR_RID (status), (int)G_SCD_BERR_DCODE(status)); +#ifdef DUMP_L2_ECC_TAG_ON_ERROR +prom_printf ("Last L2 tag w/ bad ECC: %016llx\n" , l2_tag); +#endif }else {prom_printf ("Bus watcher indicates no error\n" ); }
@@ -166,6 +181,16 @@uint64_t cerr_dpa;uint32_t errctl, cerr_i, cerr_d, dpalo, dpahi, eepc, res; +#ifdef CONFIG_SIBYTE_BW_TRACE +/* Freeze the trace buffer now */ +#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) +csr_out32 (M_BCM1480_SCD_TRACE_CFG_FREEZE ,IO_SPACE_BASE |A_SCD_TRACE_CFG ); +#else +csr_out32 (M_SCD_TRACE_CFG_FREEZE ,IO_SPACE_BASE |A_SCD_TRACE_CFG ); +#endif +prom_printf ("Trace buffer frozen\n" ); +#endif +prom_printf ("Cache error exception on CPU %x:\n" , (read_c0_prid () >>25 ) &0x7 );
@@ -229,11 +254,19 @@check_bus_watcher (); -while (1 );/* -* This tends to make things get really ugly; let's just stall instead. -* panic("Can't handle the cache error!"); +* Calling panic() when a fatal cache error occurs scrambles the +* state of the system (and the cache), making it difficult to +* investigate after the fact. However, if you just stall the CPU, +* the other CPU may keep on running, which is typically very +* undesirable. */ +#ifdef CONFIG_SB1_CERR_STALL +while (1 ) + ; +#else +panic ("unhandled cache error" ); +#endif }
@@ -434,7 +467,8 @@ };#define DC_TAG_VALID (state) \ - (((state) == 0xf) || ((state) == 0x13) || ((state) == 0x19) || ((state == 0x16)) || ((state) == 0x1c)) + (((state) == 0x0) || ((state) == 0xf) || ((state) == 0x13) || \ + ((state) == 0x19) || ((state) == 0x16) || ((state) == 0x1c))static char *dc_state_str (unsigned char state) {
@@ -505,6 +539,7 @@uint64_t datalo;uint32_t datalohi, datalolo, datahi;int offset; +char bad_ecc =0 ;for (offset =0 ; offset <4 ; offset++) {/* Index-load-data-D */
@@ -525,8 +560,7 @@ ecc =dc_ecc (datalo);if (ecc != datahi) {int bits =0 ; -prom_printf (" ** bad ECC (%02x %02x) ->" , - datahi, ecc); + bad_ecc |=1 << (3 -offset); ecc ^= datahi;while (ecc) {if (ecc &1 ) bits++;
@@ -537,6 +571,10 @@prom_printf (" %02X-%016llX" , datahi, datalo); }prom_printf ("\n" ); +if (bad_ecc) +prom_printf (" dwords w/ bad ECC: %d %d %d %d\n" , + !!(bad_ecc &8 ), !!(bad_ecc &4 ), + !!(bad_ecc &2 ), !!(bad_ecc &1 )); } }return res;
arch/mips/mm/cex-sb1.S +5 -0
@@ -64,6 +64,10 @@ sd k0,0x170($0) sd k1,0x178($0) +#if CONFIG_SB1_CEX_ALWAYS_FATAL + j handle_vec2_sb1 + nop +#else /* * M_ERRCTL_RECOVERABLE is bit 31, which makes it easy to tell * if we can fast-path out of here for a h/w-recovered error.
@@ -134,6 +138,7 @@ /* Unrecoverable Icache or Dcache error; log it and/or fail */ j handle_vec2_sb1 nop +#endif END(except_vec2_sb1)
arch/mips/sibyte/Kconfig +8 -0
@@ -102,6 +102,14 @@ Build a kernel suitable for running under the GDB simulator. Primarily adjusts the kernel's notion of time. +config CONFIG_SB1_CEX_ALWAYS_FATAL + bool "All cache exceptions considered fatal (no recovery attempted)" + depends on SIBYTE_SB1xxx_SOC + +config CONFIG_SB1_CERR_STALL + bool "Stall (rather than panic) on fatal cache error" + depends on SIBYTE_SB1xxx_SOC + config SIBYTE_CFE bool "Booting from CFE" depends on SIBYTE_SB1xxx_SOC
PATCH 8/12 cerr-printk-not-prom-printf
In reply to Andrew IsaacsonUse printk rather than prom_printf in cache error handlers. prom_printf does not handle SMP locking, and shows up only on console (not in dmesg(1) or syslog).
Signed-off-by Andy Isaacson <[email protected]>
arch/mips/mm/cerr-sb1.c | 122 ++++++++++++++++++++++++------------------------ 1 files changed, 61 insertions(+), 61 deletions(-)
arch/mips/mm/cerr-sb1.c +61 -61
@@ -78,66 +78,66 @@static inline void breakout_errctl (unsigned int val) {if (val &CP0_ERRCTL_RECOVERABLE ) -prom_printf (" recoverable" ); +printk (" recoverable" );if (val &CP0_ERRCTL_DCACHE ) -prom_printf (" dcache" ); +printk (" dcache" );if (val &CP0_ERRCTL_ICACHE ) -prom_printf (" icache" ); +printk (" icache" );if (val &CP0_ERRCTL_MULTIBUS ) -prom_printf (" multiple-buserr" ); -prom_printf ("\n" ); +printk (" multiple-buserr" ); +printk ("\n" ); }static inline void breakout_cerri (unsigned int val) {if (val &CP0_CERRI_TAG_PARITY ) -prom_printf (" tag-parity" ); +printk (" tag-parity" );if (val &CP0_CERRI_DATA_PARITY ) -prom_printf (" data-parity" ); +printk (" data-parity" );if (val &CP0_CERRI_EXTERNAL ) -prom_printf (" external" ); -prom_printf ("\n" ); +printk (" external" ); +printk ("\n" ); }static inline void breakout_cerrd (unsigned int val) {switch (val &CP0_CERRD_CAUSES ) {case CP0_CERRD_LOAD : -prom_printf (" load," ); +printk (" load," );break ;case CP0_CERRD_STORE : -prom_printf (" store," ); +printk (" store," );break ;case CP0_CERRD_FILLWB : -prom_printf (" fill/wb," ); +printk (" fill/wb," );break ;case CP0_CERRD_COHERENCY : -prom_printf (" coherency," ); +printk (" coherency," );break ;case CP0_CERRD_DUPTAG : -prom_printf (" duptags," ); +printk (" duptags," );break ;default : -prom_printf (" NO CAUSE," ); +printk (" NO CAUSE," );break ; }if (!(val &CP0_CERRD_TYPES )) -prom_printf (" NO TYPE" ); +printk (" NO TYPE" );else {if (val &CP0_CERRD_MULTIPLE ) -prom_printf (" multi-err" ); +printk (" multi-err" );if (val &CP0_CERRD_TAG_STATE ) -prom_printf (" tag-state" ); +printk (" tag-state" );if (val &CP0_CERRD_TAG_ADDRESS ) -prom_printf (" tag-address" ); +printk (" tag-address" );if (val &CP0_CERRD_DATA_SBE ) -prom_printf (" data-SBE" ); +printk (" data-SBE" );if (val &CP0_CERRD_DATA_DBE ) -prom_printf (" data-DBE" ); +printk (" data-DBE" );if (val &CP0_CERRD_EXTERNAL ) -prom_printf (" external" ); +printk (" external" ); } -prom_printf ("\n" ); +printk ("\n" ); }#ifndef CONFIG_SIBYTE_BUS_WATCHER
@@ -158,18 +158,18 @@ l2_tag =in64 (IO_SPACE_BASE |A_L2_ECC_TAG );#endif memio_err =csr_in32 (IOADDR (A_BUS_MEM_IO_ERRORS )); -prom_printf ("Bus watcher error counters: %08x %08x\n" , l2_err, memio_err); -prom_printf ("\nLast recorded signature:\n" ); -prom_printf ("Request %02x from %d, answered by %d with Dcode %d\n" , +printk ("Bus watcher error counters: %08x %08x\n" , l2_err, memio_err); +printk ("\nLast recorded signature:\n" ); +printk ("Request %02x from %d, answered by %d with Dcode %d\n" , (unsigned int )(G_SCD_BERR_TID (status) &0x3f ), (int )(G_SCD_BERR_TID (status) >>6 ), (int )G_SCD_BERR_RID (status), (int )G_SCD_BERR_DCODE (status));#ifdef DUMP_L2_ECC_TAG_ON_ERROR -prom_printf ("Last L2 tag w/ bad ECC: %016llx\n" , l2_tag); +printk ("Last L2 tag w/ bad ECC: %016llx\n" , l2_tag);#endif }else { -prom_printf ("Bus watcher indicates no error\n" ); +printk ("Bus watcher indicates no error\n" ); } }#else
@@ -184,14 +184,14 @@#ifdef CONFIG_SIBYTE_BW_TRACE /* Freeze the trace buffer now */ #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) -csr_out32 (M_BCM1480_SCD_TRACE_CFG_FREEZE ,IO_SPACE_BASE |A_SCD_TRACE_CFG ); +csr_out32 (M_BCM1480_SCD_TRACE_CFG_FREEZE ,IOADDR (A_SCD_TRACE_CFG ));#else -csr_out32 (M_SCD_TRACE_CFG_FREEZE ,IO_SPACE_BASE |A_SCD_TRACE_CFG ); +csr_out32 (M_SCD_TRACE_CFG_FREEZE ,IOADDR (A_SCD_TRACE_CFG ));#endif -prom_printf ("Trace buffer frozen\n" ); +printk ("Trace buffer frozen\n" );#endif -prom_printf ("Cache error exception on CPU %x:\n" , +printk ("Cache error exception on CPU %x:\n" , (read_c0_prid () >>25 ) &0x7 ); __asm__ __volatile__ (
@@ -210,43 +210,43 @@ "=r" (dpahi), "=r" (dpalo), "=r" (eepc)); cerr_dpa = (((uint64_t )dpahi) <<32 ) | dpalo; -prom_printf (" c0_errorepc == %08x\n" , eepc); -prom_printf (" c0_errctl == %08x" , errctl); +printk (" c0_errorepc == %08x\n" , eepc); +printk (" c0_errctl == %08x" , errctl);breakout_errctl (errctl);if (errctl &CP0_ERRCTL_ICACHE ) { -prom_printf (" c0_cerr_i == %08x" , cerr_i); +printk (" c0_cerr_i == %08x" , cerr_i);breakout_cerri (cerr_i);if (CP0_CERRI_IDX_VALID (cerr_i)) {/* Check index of EPC, allowing for delay slot */ if (((eepc &SB1_CACHE_INDEX_MASK ) != (cerr_i &SB1_CACHE_INDEX_MASK )) && ((eepc &SB1_CACHE_INDEX_MASK ) != ((cerr_i &SB1_CACHE_INDEX_MASK ) -4 ))) -prom_printf (" cerr_i idx doesn't match eepc\n" ); +printk (" cerr_i idx doesn't match eepc\n" );else { res =extract_ic (cerr_i &SB1_CACHE_INDEX_MASK , (cerr_i &CP0_CERRI_DATA ) !=0 );if (!(res & cerr_i)) -prom_printf ("...didn't see indicated icache problem\n" ); +printk ("...didn't see indicated icache problem\n" ); } } }if (errctl &CP0_ERRCTL_DCACHE ) { -prom_printf (" c0_cerr_d == %08x" , cerr_d); +printk (" c0_cerr_d == %08x" , cerr_d);breakout_cerrd (cerr_d);if (CP0_CERRD_DPA_VALID (cerr_d)) { -prom_printf (" c0_cerr_dpa == %010llx\n" , cerr_dpa); +printk (" c0_cerr_dpa == %010llx\n" , cerr_dpa);if (!CP0_CERRD_IDX_VALID (cerr_d)) { res =extract_dc (cerr_dpa &SB1_CACHE_INDEX_MASK , (cerr_d &CP0_CERRD_DATA ) !=0 );if (!(res & cerr_d)) -prom_printf ("...didn't see indicated dcache problem\n" ); +printk ("...didn't see indicated dcache problem\n" ); }else {if ((cerr_dpa &SB1_CACHE_INDEX_MASK ) != (cerr_d &SB1_CACHE_INDEX_MASK )) -prom_printf (" cerr_d idx doesn't match cerr_dpa\n" ); +printk (" cerr_d idx doesn't match cerr_dpa\n" );else { res =extract_dc (cerr_d &SB1_CACHE_INDEX_MASK , (cerr_d &CP0_CERRD_DATA ) !=0 );if (!(res & cerr_d)) -prom_printf ("...didn't see indicated problem\n" ); +printk ("...didn't see indicated problem\n" ); } } }
@@ -335,7 +335,7 @@uint8_t lru;int res =0 ; -prom_printf ("Icache index 0x%04x " , addr); +printk ("Icache index 0x%04x " , addr);for (way =0 ; way <4 ; way++) {/* Index-load-tag-I */ __asm__ __volatile__ (
@@ -355,7 +355,7 @@ taglo = ((unsigned long long )taglohi <<32 ) | taglolo;if (way ==0 ) { lru = (taghi >>14 ) &0xff ; - prom_printf("[Bank %d Set 0x%02x] LRU > %d %d %d %d > MRU\n", + printk("[Bank %d Set 0x%02x] LRU > %d %d %d %d > MRU\n", ((addr >> 5) & 0x3), /* bank */ ((addr >> 7) & 0x3f), /* index */ (lru & 0x3),
@@ -370,19 +370,19 @@if (valid) { tlo_tmp = taglo &0xfff3ff ;if (((taglo >>10 ) &1 ) ^range_parity (tlo_tmp,23 ,0 )) { -prom_printf (" ** bad parity in VTag0/G/ASID\n" ); +printk (" ** bad parity in VTag0/G/ASID\n" ); res |=CP0_CERRI_TAG_PARITY ; }if (((taglo >>11 ) &1 ) ^range_parity (taglo,63 ,24 )) { -prom_printf (" ** bad parity in R/VTag1\n" ); +printk (" ** bad parity in R/VTag1\n" ); res |=CP0_CERRI_TAG_PARITY ; } }if (valid ^ ((taghi >>27 ) &1 )) { -prom_printf (" ** bad parity for valid bit\n" ); +printk (" ** bad parity for valid bit\n" ); res |=CP0_CERRI_TAG_PARITY ; } -prom_printf (" %d [VA %016llx] [Vld? %d] raw tags: %08X-%016llX\n" , +printk (" %d [VA %016llx] [Vld? %d] raw tags: %08X-%016llX\n" , way, va, valid, taghi, taglo);if (data) {
@@ -408,21 +408,21 @@ : "r" ((way << 13) | addr | (offset << 3))); predecode = (datahi >>8 ) &0xff ;if (((datahi >>16 ) &1 ) != (uint32_t )range_parity (predecode,7 ,0 )) { -prom_printf (" ** bad parity in predecode\n" ); +printk (" ** bad parity in predecode\n" ); res |=CP0_CERRI_DATA_PARITY ; }/* XXXKW should/could check predecode bits themselves */ if (((datahi >>4 ) &0xf ) ^inst_parity (insta)) { -prom_printf (" ** bad parity in instruction a\n" ); +printk (" ** bad parity in instruction a\n" ); res |=CP0_CERRI_DATA_PARITY ; }if ((datahi &0xf ) ^inst_parity (instb)) { -prom_printf (" ** bad parity in instruction b\n" ); +printk (" ** bad parity in instruction b\n" ); res |=CP0_CERRI_DATA_PARITY ; } -prom_printf (" %05X-%08X%08X" , datahi, insta, instb); +printk (" %05X-%08X%08X" , datahi, insta, instb); } -prom_printf ("\n" ); +printk ("\n" ); } }return res;
@@ -490,7 +490,7 @@uint8_t ecc, lru;int res =0 ; -prom_printf ("Dcache index 0x%04x " , addr); +printk ("Dcache index 0x%04x " , addr);for (way =0 ; way <4 ; way++) { __asm__ __volatile__ ( " .set push\n\t"
@@ -510,7 +510,7 @@ pa = (taglo &0xFFFFFFE000ULL ) | addr;if (way ==0 ) { lru = (taghi >>14 ) &0xff ; - prom_printf("[Bank %d Set 0x%02x] LRU > %d %d %d %d > MRU\n", + printk("[Bank %d Set 0x%02x] LRU > %d %d %d %d > MRU\n", ((addr >> 11) & 0x2) | ((addr >> 5) & 1), /* bank */ ((addr >> 6) & 0x3f), /* index */ (lru & 0x3),
@@ -520,15 +520,15 @@ } state = (taghi >>25 ) &0x1f ; valid =DC_TAG_VALID (state); -prom_printf (" %d [PA %010llx] [state %s (%02x)] raw tags: %08X-%016llX\n" , +printk (" %d [PA %010llx] [state %s (%02x)] raw tags: %08X-%016llX\n" , way, pa,dc_state_str (state), state, taghi, taglo);if (valid) {if (((taglo >>11 ) &1 ) ^range_parity (taglo,39 ,26 )) { -prom_printf (" ** bad parity in PTag1\n" ); +printk (" ** bad parity in PTag1\n" ); res |=CP0_CERRD_TAG_ADDRESS ; }if (((taglo >>10 ) &1 ) ^range_parity (taglo,25 ,13 )) { -prom_printf (" ** bad parity in PTag0\n" ); +printk (" ** bad parity in PTag0\n" ); res |=CP0_CERRD_TAG_ADDRESS ; } }else {
@@ -568,11 +568,11 @@ } res |= (bits ==1 ) ?CP0_CERRD_DATA_SBE :CP0_CERRD_DATA_DBE ; } -prom_printf (" %02X-%016llX" , datahi, datalo); +printk (" %02X-%016llX" , datahi, datalo); } -prom_printf ("\n" ); +printk ("\n" );if (bad_ecc) -prom_printf (" dwords w/ bad ECC: %d %d %d %d\n" , +printk (" dwords w/ bad ECC: %d %d %d %d\n" , !!(bad_ecc &8 ), !!(bad_ecc &4 ), !!(bad_ecc &2 ), !!(bad_ecc &1 )); }
Re: [PATCH 8/12] cerr-printk-not-prom-printf
Quoted 3 lines · Andrew Isaacson
Use printk rather than
prom_printfin cache error handlers.prom_printfdoes not handle SMP locking, and shows up only on console (not in dmesg(1) or syslog).
This patch essentially reverses
(Yuck, gitk URLs are bloody long ...)
The reason for this old commit was that this code is running uncached, so the operation of ll/sc in the spinlocks is undefined according to the MIPS64 spec, also there is a potencial deadlock since printk's logbuf_lock might be held.
The old pass 1 part did truely exercise the cache error handler ;-)
Ralf
Re: [PATCH 8/12] cerr-printk-not-prom-printf
Quoted 3 lines · Ralf Baechle
The reason for this old commit was that this code is running uncached, so the operation of ll/sc in the spinlocks is undefined according to the MIPS64 spec...
The answer is more complicated. MIPS64 (elsewhere) requires that the ll/sc "link" is broken on an exceptin - in fact on an 'eret' instruction.
So ll/sc on an uncached location works just fine in a uniprocessor. However, it's unlikely that any cache-coherent mulitprocessor system will snoop uncached reads and writes, so it won't work in an SMP system.
--
Dominic
Re: [PATCH 8/12] cerr-printk-not-prom-printf
Quoted 7 lines · Dominic Sweetman
Quoted 3 lines
The reason for this old commit was that this code is running uncached, so the operation of ll/sc in the spinlocks is undefined according to the MIPS64 spec...
The answer is more complicated. MIPS64 (elsewhere) requires that the ll/sc "link" is broken on an exceptin - in fact on an 'eret' instruction.
But in case of the code in question no eret will be executed between taking the cache error exception and printk trying to take the lock.
Quoted 4 lines
So ll/sc on an uncached location works just fine in a uniprocessor. However, it's unlikely that any cache-coherent mulitprocessor system will snoop uncached reads and writes, so it won't work in an SMP system.
Fine - but at that point we could have two processors messing with the same buffers. Bad Thing (TM).
Ralf
PATCH 9/12 sbmac-fixes
In reply to Andrew IsaacsonImprove sb1250-mac driver to probe for PHYs at addresses other than 1, such as the PHYs on BigSur.
Signed-off-by Andy Isaacson <[email protected]>
drivers/net/sb1250-mac.c | 36 ++++++++++++++++++++++++++++++++++++ 1 files changed, 36 insertions(+)
drivers/net/sb1250-mac.c +36 -0
@@ -314,6 +314,7 @@static int sbmac_mii_ioctl (struct net_device *dev,struct ifreq *rq,int cmd);static int sbmac_close (struct net_device *dev);static int sbmac_mii_poll (struct sbmac_softc *s,int noisy); +static int sbmac_mii_probe (struct net_device *dev);static void sbmac_mii_sync (struct sbmac_softc *s);static void sbmac_mii_senddata (struct sbmac_softc *s,unsigned int data,int bitcnt);
@@ -451,6 +452,9 @@#define MII_BMCR 0x00/* Basic mode control register (rw) */ #define MII_BMSR 0x01/* Basic mode status register (ro) */ +#define MII_PHYIDR1 0x02 +#define MII_PHYIDR2 0x03 +#define MII_K1STSR 0x0A/* 1K Status Register (ro) */ #define MII_ANLPAR 0x05/* Autonegotiation lnk partner abilities (rw) */
@@ -2460,6 +2464,15 @@return -EBUSY ;/* +* Probe phy address +*/ + +if (sbmac_mii_probe (dev) ==-1 ) { +printk ("%s: failed to probe PHY.\n" , dev->name); +return -EINVAL ; + } + +/* * Configure default speed */
@@ -2492,6 +2505,29 @@return 0 ; } +static int sbmac_mii_probe (struct net_device *dev) +{ +int i; +struct sbmac_softc *s =netdev_priv (dev); +u16 bmsr, id1, id2; +u32 vendor, device; + +for (i=1 ; i<31 ; i++) { + bmsr =sbmac_mii_read (s, i,MII_BMSR ); +if (bmsr !=0 ) { + s->sbm_phys[0 ] = i; + id1 =sbmac_mii_read (s, i,MII_PHYIDR1 ); + id2 =sbmac_mii_read (s, i,MII_PHYIDR2 ); + vendor = ((u32 )id1 <<6 ) | ((id2 >>10 ) &0x3f ); + device = (id2 >>4 ) &0x3f ; + +printk (KERN_INFO "%s: found phy %d, vendor %06x part %02x\n" , + dev->name, i, vendor, device); +return i; + } + } +return -1 ; +}static int sbmac_mii_poll (struct sbmac_softc *s,int noisy)
PATCH 10/12 1480-pci-support
In reply to Andrew IsaacsonPCI support code for bcm1480 on-chip PCI-X bridge
Signed-off-by Andy Isaacson <[email protected]>
arch/mips/pci/Makefile | 1 arch/mips/pci/pci-bcm1480.c | 256 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 257 insertions(+)
arch/mips/pci/Makefile +1 -0
@@ -46,6 +46,7 @@ obj-$(CONFIG_SGI_IP27) += pci-ip27.o obj-$(CONFIG_SGI_IP32) += fixup-ip32.o ops-mace.o pci-ip32.o obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o +obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o obj-$(CONFIG_SNI_RM200_PCI) += fixup-sni.o ops-sni.o obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
arch/mips/pci/pci-bcm1480.c new file +256 -0
256 lines not on this page · raw message
PATCH 11/12 1480-ht-support
In reply to Andrew IsaacsonPCI support code for PLX 7250 PCI-X tunnel on BCM91480B BigSur board.
Signed-off-by Andy Isaacson <[email protected]>
arch/mips/Kconfig | 1 arch/mips/pci/Makefile | 2 arch/mips/pci/pci-bcm1480.c | 21 ++- arch/mips/pci/pci-bcm1480ht.c | 224 ++++++++++++++++++++++++++++++++++++++++++ arch/mips/pci/pci.c | 17 ++- include/asm-mips/pci.h | 5 6 files changed, 253 insertions(+), 17 deletions(-)
arch/mips/pci/pci-bcm1480.c +11 -10
@@ -56,13 +56,11 @@static void *cfg_space;#define PCI_BUS_ENABLED 1 -#define LDT_BUS_ENABLED 2 -#define PCI_DEVICE_MODE 4 +#define PCI_DEVICE_MODE 2static int bcm1480_bus_status =0 ;#define PCI_BRIDGE_DEVICE 0 -#define LDT_BRIDGE_DEVICE 1/* * Read/write 32-bit values in config space.
@@ -95,10 +93,13 @@*/ static int bcm1480_pci_can_access (struct pci_bus *bus,int devfn) { +u32 devno; +if (!(bcm1480_bus_status & (PCI_BUS_ENABLED |PCI_DEVICE_MODE )))return 0 ;if (bus->number ==0 ) { + devno =PCI_SLOT (devfn);if (bcm1480_bus_status &PCI_DEVICE_MODE )return 0 ;else
@@ -175,15 +176,15 @@static struct resource bcm1480_mem_resource = { .name ="BCM1480 PCI MEM" , - .start =0x40000000UL , - .end =0x5fffffffUL , + .start =0x30000000UL , + .end =0x3fffffffUL , .flags =IORESOURCE_MEM , };static struct resource bcm1480_io_resource = { .name ="BCM1480 PCI I/O" , - .start =0x00000000UL , - .end =0x01ffffffUL , + .start =0x2c000000UL , + .end =0x2dffffffUL , .flags =IORESOURCE_IO , };
@@ -207,9 +208,9 @@PCIBIOS_MIN_IO =0x00008000UL ;PCIBIOS_MIN_MEM =0x01000000UL ; -/* Set I/O resource limits. */ - ioport_resource.end =0x01ffffffUL ;/* 32MB accessible by bcm1480 */ - iomem_resource.end =0xffffffffUL ;/* no HT support yet */ +/* Set I/O resource limits. - unlimited for now to accomodate HT */ + ioport_resource.end =0xffffffffUL ; + iomem_resource.end =0xffffffffUL ; cfg_space =ioremap (A_BCM1480_PHYS_PCI_CFG_MATCH_BITS ,16 *1024 *1024 );
arch/mips/Kconfig +1 -0
@@ -552,6 +552,7 @@ select SWAP_IO_SPACE select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN + select PCI_DOMAINS config SIBYTE_SWARM bool "Support for Sibyte BCM91250A-SWARM"
arch/mips/pci/Makefile +1 -1
@@ -46,7 +46,7 @@ obj-$(CONFIG_SGI_IP27) += pci-ip27.o obj-$(CONFIG_SGI_IP32) += fixup-ip32.o ops-mace.o pci-ip32.o obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o -obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o +obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o obj-$(CONFIG_SNI_RM200_PCI) += fixup-sni.o ops-sni.o obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
arch/mips/pci/pci-bcm1480ht.c new file +224 -0
224 lines not on this page · raw message
arch/mips/pci/pci.c +11 -6
@@ -127,15 +127,20 @@if (!hose->iommu)PCI_DMA_BUS_IS_PHYS =1 ; +if (hose->get_busno && pci_probe_only) + next_busno = (*hose->get_busno)(); + bus =pci_scan_bus (next_busno, hose->pci_ops, hose); hose->bus = bus; hose->need_domain_info = need_domain_info; - next_busno = bus->subordinate +1 ; -/* Don't allow 8-bit bus number overflow inside the hose - -reserve some space for bridges. */ -if (next_busno >224 ) { - next_busno =0 ; - need_domain_info =1 ; +if (bus) { + next_busno = bus->subordinate +1 ; +/* Don't allow 8-bit bus number overflow inside the hose - +reserve some space for bridges. */ +if (next_busno >224 ) { + next_busno =0 ; + need_domain_info =1 ; + } }continue ;
include/asm-mips/pci.h +5 -0
@@ -40,6 +40,11 @@unsigned int need_domain_info;int iommu; + +/* Optional access methods for reading/writing the bus number +of the PCI controller */ +int (*get_busno)(void ); +void (*set_busno)(int busno); };/*
PATCH 12/12 pci-expmem-hack
In reply to Andrew IsaacsonCFE 1.2.5 and earlier fails to turn on the ExpMemEn bit in the PCIFeatureControl register, which means that DMA does not work beyond physical address 01_0000_0000, ergo to DRAM beyond 1GB.
With ExpMemEn turned on, 01_0000_0000-0f_ffff_ffff is mapped, so DMA works for up to 61 GB of DRAM.
Will be fixed in CFE 1.2.6 (yet to be released).
Signed-off-by Andy Isaacson <[email protected]>
arch/mips/pci/pci-bcm1480.c | 8 ++++++++ 1 files changed, 8 insertions(+)
arch/mips/pci/pci-bcm1480.c +8 -0
@@ -232,6 +232,14 @@ bcm1480_bus_status |=PCI_BUS_ENABLED ; } +/* turn on ExpMemEn */ + cmdreg =READCFG32 (CFGOFFSET (0 ,PCI_DEVFN (PCI_BRIDGE_DEVICE ,0 ),0x40 )); +printk ("PCIFeatureCtrl = %x\n" , cmdreg); +WRITECFG32 (CFGOFFSET (0 ,PCI_DEVFN (PCI_BRIDGE_DEVICE ,0 ),0x40 ), + cmdreg |0x10 ); + cmdreg =READCFG32 (CFGOFFSET (0 ,PCI_DEVFN (PCI_BRIDGE_DEVICE ,0 ),0x40 )); +printk ("PCIFeatureCtrl = %x\n" , cmdreg); +/* * Establish mappings in KSEG2 (kernel virtual) to PCI I/O * space. Use "match bytes" policy to make everything look