Make PPC7450Features useable

PATCH In review Rupert Eibauer 2 participants 7 messages Oct 21, 2005

lore

Share & tools

lore

Rupert Eibauer

author

2005-10-21 13:02 UTC #0 lore raw

PATCH 1/1 Make PPC7450Features useable

(Please CC to me, I am not subscribed)

Hello,

This patch makes 3 of the 7450 features useable. These are:

- High BAT (BATs 4-7)
- Extended BAT Block Size (In this mode a BAT can cover up to 4GB)
- 36-Bit Physical addressing with BATs

I was able to test the High BAT and the 36-Bit addressing on a 7447A, for the large BAT, I don't have enough memory. Maybe somebody with at least 512 MB of memory should test it.

I don't have much experience in submitting, kernel patches, so if there is anything wrong with my patch, please point it out.

However, I did not manage to adjust the page tables to do the same trick (36-Bit Addressing). The page tables seem a lot more magic to me.

Here is the patch:

arch/ppc/Kconfig +16 -2

diff -urN linux-2.6.13.3.orig/arch/ppc/Kconfig linux-2.6.13.3/arch/ppc/Kconfig
@@ -115,14 +115,28 @@
 	default y if E500 && PHYS_64BIT
 
 config PHYS_64BIT
-	bool 'Large physical address support' if E500
-	depends on 44x || E500
+	bool 'Large physical address support' if E500 || 6xx
+	depends on 44x || E500 || 6xx
 	default y if 44x
 	---help---
 	  This option enables kernel support for larger than 32-bit physical
 	  addresses.  This features is not be available on all e500 cores.
 
 	  If in doubt, say N here.
+
+config PPC_LARGE_BATS
+	bool 'Extended BAT Block Bize Support' if 6xx
+	depends on 6xx
+	---help---
+	 This option enables kernel support for large BAT
+	 addressing mode, which is present on some 7450 chips.
+
+config PPC_HIGH_BATS
+	bool 'High BAT Support' if 6xx
+	depends on 6xx
+	---help---
+	 This option enables kernel support for the 4 additional
+	 BATS, which is present on some 7450 chips.
 
 config ALTIVEC
 	bool "AltiVec Support"

arch/ppc/kernel/cpu_setup_6xx.S +7 -1

diff -urN linux-2.6.13.3.orig/arch/ppc/kernel/cpu_setup_6xx.S linux-2.6.13.3/arch/ppc/kernel/cpu_setup_6xx.S
@@ -229,13 +229,19 @@
 	 */
 	ori	r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE
 	ori	r11,r11,HID0_LRSTK | HID0_BTIC
-	oris	r11,r11,HID0_DPM@h
+	oris	r11,r11,HID0_DPM@h | HID0_XAEN@h
 BEGIN_FTR_SECTION
 	xori	r11,r11,HID0_BTIC
 END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC)
 BEGIN_FTR_SECTION
 	xoris	r11,r11,HID0_DPM@h	/* disable dynamic power mgmt */
 END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
+BEGIN_FTR_SECTION
+	xoris	r11,r11,HID0_XAEN@h
+END_FTR_SECTION_IFCLR(CPU_FTR_BIG_PHYS)
+BEGIN_FTR_SECTION
+	ori	r11,r11,HID0_XBSEN
+END_FTR_SECTION_IFSET(CPU_FTR_LARGE_BATS)
 
 	/* All of the bits we have to clear....
 	 */

arch/ppc/kernel/cputable.c +19 -0

diff -urN linux-2.6.13.3.orig/arch/ppc/kernel/cputable.c linux-2.6.13.3/arch/ppc/kernel/cputable.c
@@ -62,6 +62,18 @@
 #define PPC_FEATURE_SPE_COMP       	0
 #endif
 
+#ifdef CONFIG_PPC_LARGE_BATS
+#define CPU_FTR_LARGE_BATS_COMP		CPU_FTR_LARGE_BATS
+#else
+#define CPU_FTR_LARGE_BATS_COMP		0
+#endif
+
+#ifndef CONFIG_PHYS_64BIT
+#define CPU_FTR_BIG_PHYS_COMP		CPU_FTR_BIG_PHYS
+#else
+#define CPU_FTR_BIG_PHYS_COMP		0
+#endif
+
 /* We need to mark all pages as being coherent if we're SMP or we
  * have a 74[45]x and an MPC107 host bridge.
  */

@@ -428,6 +440,7 @@
 			CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 			CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 			CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+			CPU_FTR_BIG_PHYS_COMP | CPU_FTR_LARGE_BATS_COMP |
 			CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
 		.cpu_user_features	= COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 		.icache_bsize		= 32,

@@ -445,6 +458,7 @@
 			CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 			CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 			CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
+			CPU_FTR_BIG_PHYS_COMP | CPU_FTR_LARGE_BATS_COMP |
 			CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
 		.cpu_user_features	= COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 		.icache_bsize		= 32,

@@ -462,6 +476,7 @@
 			CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 			CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 			CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+			CPU_FTR_BIG_PHYS_COMP | CPU_FTR_LARGE_BATS_COMP |
 			CPU_FTR_NEED_COHERENT,
 		.cpu_user_features	= COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 		.icache_bsize		= 32,

@@ -478,6 +493,7 @@
 			CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
 			CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 			CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+			CPU_FTR_BIG_PHYS_COMP | CPU_FTR_LARGE_BATS_COMP |
 			CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
 			CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
 		.cpu_user_features	= COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,

@@ -496,6 +512,7 @@
 			CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 			CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 			CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+			CPU_FTR_BIG_PHYS_COMP | CPU_FTR_LARGE_BATS_COMP |
 			CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
 		.cpu_user_features	= COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 		.icache_bsize		= 32,

@@ -513,6 +530,7 @@
 			CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 			CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 			CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+			CPU_FTR_BIG_PHYS_COMP | CPU_FTR_LARGE_BATS_COMP |
 			CPU_FTR_NEED_COHERENT,
 		.cpu_user_features	= COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 		.icache_bsize		= 32,

@@ -529,6 +547,7 @@
 			CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
 			CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
 			CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
+			CPU_FTR_BIG_PHYS_COMP | CPU_FTR_LARGE_BATS_COMP |
 			CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
 		.cpu_user_features	= COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 		.icache_bsize		= 32,

arch/ppc/kernel/head.S +8 -0

diff -urN linux-2.6.13.3.orig/arch/ppc/kernel/head.S linux-2.6.13.3/arch/ppc/kernel/head.S
@@ -1165,6 +1165,14 @@
 	LOAD_BAT(1,r3,r4,r5)
 	LOAD_BAT(2,r3,r4,r5)
 	LOAD_BAT(3,r3,r4,r5)
+#ifdef CONFIG_PPC_HIGH_BATS
+BEGIN_FTR_SECTION
+	LOAD_BAT(4,r3,r4,r5)
+	LOAD_BAT(5,r3,r4,r5)
+	LOAD_BAT(6,r3,r4,r5)
+	LOAD_BAT(7,r3,r4,r5)
+END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
+#endif /* CONFIG_PPC_HIGH_BATS */
 #endif /* CONFIG_POWER4 */
 	blr

arch/ppc/mm/pgtable.c +3 -3

diff -urN linux-2.6.13.3.orig/arch/ppc/mm/pgtable.c linux-2.6.13.3/arch/ppc/mm/pgtable.c
@@ -55,8 +55,8 @@
 
 #ifdef HAVE_BATS
 extern unsigned long v_mapped_by_bats(unsigned long va);
-extern unsigned long p_mapped_by_bats(unsigned long pa);
-void setbat(int index, unsigned long virt, unsigned long phys,
+extern unsigned long p_mapped_by_bats(phys_addr_t pa);
+void setbat(int index, unsigned long virt, phys_addr_t phys,
 	    unsigned int size, int flags);
 
 #else /* !HAVE_BATS */

@@ -339,7 +339,7 @@
 	/*
 	 * Use a BAT for this if possible...
 	 */
-	if (io_bat_index < 2 && is_power_of_2(size)
+	if (io_bat_index < (ppc_bat_count() - 2) && is_power_of_2(size)
 	    && (virt & (size - 1)) == 0 && (phys & (size - 1)) == 0) {
 		setbat(io_bat_index, virt, phys, size, flags);
 		++io_bat_index;

arch/ppc/mm/ppc_mmu.c +21 ~~-15~~

diff -urN linux-2.6.13.3.orig/arch/ppc/mm/ppc_mmu.c linux-2.6.13.3/arch/ppc/mm/ppc_mmu.c
@@ -36,6 +36,7 @@
 #include "mmu_decl.h"
 #include "mem_pieces.h"
 
+
 PTE *Hash, *Hash_end;
 unsigned long Hash_size, Hash_mask;
 unsigned long _SDR1;

@@ -47,13 +48,13 @@
 #else
 	u32	word[2];
 #endif
-} BATS[4][2];			/* 4 pairs of IBAT, DBAT */
+} BATS[PPC_BAT_COUNT][2];			/* 4 pairs of IBAT, DBAT */
 
 struct batrange {		/* stores address ranges mapped by BATs */
 	unsigned long start;
 	unsigned long limit;
-	unsigned long phys;
-} bat_addrs[4];
+	phys_addr_t phys;
+} bat_addrs[PPC_BAT_COUNT];
 
 /*
  * Return PA for this VA if it is mapped by a BAT, or 0

@@ -61,7 +62,7 @@
 unsigned long v_mapped_by_bats(unsigned long va)
 {
 	int b;
-	for (b = 0; b < 4; ++b)
+	for (b = 0; b < PPC_BAT_COUNT; ++b)
 		if (va >= bat_addrs[b].start && va < bat_addrs[b].limit)
 			return bat_addrs[b].phys + (va - bat_addrs[b].start);
 	return 0;

@@ -70,10 +71,10 @@
 /*
  * Return VA for a given PA or 0 if not mapped
  */
-unsigned long p_mapped_by_bats(unsigned long pa)
+unsigned long p_mapped_by_bats(phys_addr_t pa)
 {
 	int b;
-	for (b = 0; b < 4; ++b)
+	for (b = 0; b < PPC_BAT_COUNT; ++b)
 		if (pa >= bat_addrs[b].phys
 	    	    && pa < (bat_addrs[b].limit-bat_addrs[b].start)
 		              +bat_addrs[b].phys)

@@ -87,13 +88,14 @@
 	return 0;
 #else
 	unsigned long tot, bl, done;
-	unsigned long max_size = (256<<20);
+	unsigned long max_size = max_bat_size();
 	unsigned long align;
+	int bat_nbr = ppc_bat_count() - 2;
 
 	if (__map_without_bats)
 		return 0;
 
-	/* Set up BAT2 and if necessary BAT3 to cover RAM. */
+	/* Set up BAT[2|6] and if necessary BAT[3|7] to cover RAM. */
 
 	/* Make sure we don't map a block larger than the
 	   smallest alignment of the physical address. */

@@ -109,16 +111,17 @@
 			break;
 	}
 
-	setbat(2, KERNELBASE, PPC_MEMSTART, bl, _PAGE_RAM);
-	done = (unsigned long)bat_addrs[2].limit - KERNELBASE + 1;
-	if ((done < tot) && !bat_addrs[3].limit) {
-		/* use BAT3 to cover a bit more */
+	setbat(bat_nbr, KERNELBASE, PPC_MEMSTART, bl, _PAGE_RAM);
+	done = (unsigned long)bat_addrs[bat_nbr].limit - KERNELBASE + 1;
+	bat_nbr++;
+	if ((done < tot) && !bat_addrs[bat_nbr].limit) {
+		/* use BAT[3|7] to cover a bit more */
 		tot -= done;
 		for (bl = 128<<10; bl < max_size; bl <<= 1)
 			if (bl * 2 > tot)
 				break;
-		setbat(3, KERNELBASE+done, PPC_MEMSTART+done, bl, _PAGE_RAM);
-		done = (unsigned long)bat_addrs[3].limit - KERNELBASE + 1;
+		setbat(bat_nbr, KERNELBASE+done, PPC_MEMSTART+done, bl, _PAGE_RAM);
+		done = (unsigned long)bat_addrs[bat_nbr].limit - KERNELBASE + 1;
 	}
 
 	return done;

@@ -130,7 +133,7 @@
  * The parameters are not checked; in particular size must be a power
  * of 2 between 128k and 256M.
  */
-void __init setbat(int index, unsigned long virt, unsigned long phys,
+void __init setbat(int index, unsigned long virt, phys_addr_t phys,
 		   unsigned int size, int flags)
 {
 	unsigned int bl;

@@ -148,6 +151,9 @@
 		wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
 				   | _PAGE_COHERENT | _PAGE_GUARDED);
 		wimgxpp |= (flags & _PAGE_RW)? BPP_RW: BPP_RX;
+#ifdef CONFIG_PHYS_64BIT
+		wimgxpp |= ((phys >> 30) & 4) | ((phys >> 24) & 0xe00);
+#endif
 		bat[1].word[0] = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */
 		bat[1].word[1] = phys | wimgxpp;
 #ifndef CONFIG_KGDB /* want user access for breakpoints */

include/asm-ppc/cputable.h +1 -0

diff -urN linux-2.6.13.3.orig/include/asm-ppc/cputable.h linux-2.6.13.3/include/asm-ppc/cputable.h
@@ -89,6 +89,7 @@
 #define CPU_FTR_NEED_COHERENT		0x00020000
 #define CPU_FTR_NO_BTIC			0x00040000
 #define CPU_FTR_BIG_PHYS		0x00080000
+#define CPU_FTR_LARGE_BATS		0x00100000
 
 #ifdef __ASSEMBLY__

include/asm-ppc/mmu.h +19 -0

diff -urN linux-2.6.13.3.orig/include/asm-ppc/mmu.h linux-2.6.13.3/include/asm-ppc/mmu.h
@@ -18,11 +18,30 @@
 #ifndef CONFIG_PHYS_64BIT
 typedef unsigned long phys_addr_t;
 #define PHYS_FMT	"%.8lx"
+#define cpu_has_bigphys() 0
 #else
 typedef unsigned long long phys_addr_t;
 extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t);
 #define PHYS_FMT	"%16Lx"
+#define cpu_has_bigphys() cpu_has_feature(CPU_FTR_BIG_PHYS)
 #endif
+
+#ifdef CONFIG_PPC_LARGE_BATS
+/* We don't allow 4G Bat's because it doesn't fit into size_t */
+#define max_bat_size() (cpu_has_feature(CPU_FTR_LARGE_BATS)?(2<<30):(256<<20))
+#else
+#define max_bat_size() (256<<20)
+#endif
+
+/* High BAT support */
+#ifdef CONFIG_PPC_HIGH_BATS
+#define PPC_BAT_COUNT 8
+#define ppc_bat_count() (cpu_has_feature(CPU_FTR_HAS_HIGH_BATS)?8:4)
+#else
+#define PPC_BAT_COUNT 4
+#define ppc_bat_count() (4)
+#endif
+
 
 /* Default "unsigned long" context */
 typedef unsigned long mm_context_t;

Rupert Eibauer

author

2005-10-21 12:27 UTC #1 lore raw

Re: [PATCH][RFT] please use this one

Hello,

Please try this one. The first one contained a last-second fix which I didn't test if it compiles.

Regards,
Rupert

arch/ppc/Kconfig +16 -2

diff -urN linux-2.6.13.3.orig/arch/ppc/Kconfig linux-2.6.13.3/arch/ppc/Kconfig
@@ -115,14 +115,28 @@
 	default y if E500 && PHYS_64BIT
 
 config PHYS_64BIT
-	bool 'Large physical address support' if E500
-	depends on 44x || E500
+	bool 'Large physical address support' if E500 || 6xx
+	depends on 44x || E500 || 6xx
 	default y if 44x
 	---help---
 	  This option enables kernel support for larger than 32-bit physical
 	  addresses.  This features is not be available on all e500 cores.
 
 	  If in doubt, say N here.
+
+config PPC_LARGE_BATS
+	bool 'Extended BAT Block Bize Support' if 6xx
+	depends on 6xx
+	---help---
+	 This option enables kernel support for large BAT
+	 addressing mode, which is present on some 7450 chips.
+
+config PPC_HIGH_BATS
+	bool 'High BAT Support' if 6xx
+	depends on 6xx
+	---help---
+	 This option enables kernel support for the 4 additional
+	 BATS, which is present on some 7450 chips.
 
 config ALTIVEC
 	bool "AltiVec Support"

arch/ppc/kernel/cpu_setup_6xx.S +7 -1

diff -urN linux-2.6.13.3.orig/arch/ppc/kernel/cpu_setup_6xx.S linux-2.6.13.3/arch/ppc/kernel/cpu_setup_6xx.S
@@ -229,13 +229,19 @@
 	 */
 	ori	r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE
 	ori	r11,r11,HID0_LRSTK | HID0_BTIC
-	oris	r11,r11,HID0_DPM@h
+	oris	r11,r11,(HID0_DPM | HID0_XAEN)@h
 BEGIN_FTR_SECTION
 	xori	r11,r11,HID0_BTIC
 END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC)
 BEGIN_FTR_SECTION
 	xoris	r11,r11,HID0_DPM@h	/* disable dynamic power mgmt */
 END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
+BEGIN_FTR_SECTION
+	xoris	r11,r11,HID0_XAEN@h
+END_FTR_SECTION_IFCLR(CPU_FTR_BIG_PHYS)
+BEGIN_FTR_SECTION
+	ori	r11,r11,HID0_XBSEN
+END_FTR_SECTION_IFSET(CPU_FTR_LARGE_BATS)
 
 	/* All of the bits we have to clear....
 	 */

arch/ppc/kernel/cputable.c +19 -0

diff -urN linux-2.6.13.3.orig/arch/ppc/kernel/cputable.c linux-2.6.13.3/arch/ppc/kernel/cputable.c
@@ -62,6 +62,18 @@
 #define PPC_FEATURE_SPE_COMP       	0
 #endif
 
+#ifdef CONFIG_PPC_LARGE_BATS
+#define CPU_FTR_LARGE_BATS_COMP		CPU_FTR_LARGE_BATS
+#else
+#define CPU_FTR_LARGE_BATS_COMP		0
+#endif
+
+#ifndef CONFIG_PHYS_64BIT
+#define CPU_FTR_BIG_PHYS_COMP		CPU_FTR_BIG_PHYS
+#else
+#define CPU_FTR_BIG_PHYS_COMP		0
+#endif
+
 /* We need to mark all pages as being coherent if we're SMP or we
  * have a 74[45]x and an MPC107 host bridge.
  */

@@ -428,6 +440,7 @@
 			CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 			CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 			CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+			CPU_FTR_BIG_PHYS_COMP | CPU_FTR_LARGE_BATS_COMP |
 			CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
 		.cpu_user_features	= COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 		.icache_bsize		= 32,

@@ -445,6 +458,7 @@
 			CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 			CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 			CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
+			CPU_FTR_BIG_PHYS_COMP | CPU_FTR_LARGE_BATS_COMP |
 			CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
 		.cpu_user_features	= COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 		.icache_bsize		= 32,

@@ -462,6 +476,7 @@
 			CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 			CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 			CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+			CPU_FTR_BIG_PHYS_COMP | CPU_FTR_LARGE_BATS_COMP |
 			CPU_FTR_NEED_COHERENT,
 		.cpu_user_features	= COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 		.icache_bsize		= 32,

@@ -478,6 +493,7 @@
 			CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
 			CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 			CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+			CPU_FTR_BIG_PHYS_COMP | CPU_FTR_LARGE_BATS_COMP |
 			CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
 			CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
 		.cpu_user_features	= COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,

@@ -496,6 +512,7 @@
 			CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 			CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 			CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+			CPU_FTR_BIG_PHYS_COMP | CPU_FTR_LARGE_BATS_COMP |
 			CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
 		.cpu_user_features	= COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 		.icache_bsize		= 32,

@@ -513,6 +530,7 @@
 			CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 			CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 			CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+			CPU_FTR_BIG_PHYS_COMP | CPU_FTR_LARGE_BATS_COMP |
 			CPU_FTR_NEED_COHERENT,
 		.cpu_user_features	= COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 		.icache_bsize		= 32,

@@ -529,6 +547,7 @@
 			CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
 			CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
 			CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
+			CPU_FTR_BIG_PHYS_COMP | CPU_FTR_LARGE_BATS_COMP |
 			CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
 		.cpu_user_features	= COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 		.icache_bsize		= 32,

arch/ppc/kernel/head.S +8 -0

diff -urN linux-2.6.13.3.orig/arch/ppc/kernel/head.S linux-2.6.13.3/arch/ppc/kernel/head.S
@@ -1165,6 +1165,14 @@
 	LOAD_BAT(1,r3,r4,r5)
 	LOAD_BAT(2,r3,r4,r5)
 	LOAD_BAT(3,r3,r4,r5)
+#ifdef CONFIG_PPC_HIGH_BATS
+BEGIN_FTR_SECTION
+	LOAD_BAT(4,r3,r4,r5)
+	LOAD_BAT(5,r3,r4,r5)
+	LOAD_BAT(6,r3,r4,r5)
+	LOAD_BAT(7,r3,r4,r5)
+END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
+#endif /* CONFIG_PPC_HIGH_BATS */
 #endif /* CONFIG_POWER4 */
 	blr

arch/ppc/mm/pgtable.c +3 -3

diff -urN linux-2.6.13.3.orig/arch/ppc/mm/pgtable.c linux-2.6.13.3/arch/ppc/mm/pgtable.c
@@ -55,8 +55,8 @@
 
 #ifdef HAVE_BATS
 extern unsigned long v_mapped_by_bats(unsigned long va);
-extern unsigned long p_mapped_by_bats(unsigned long pa);
-void setbat(int index, unsigned long virt, unsigned long phys,
+extern unsigned long p_mapped_by_bats(phys_addr_t pa);
+void setbat(int index, unsigned long virt, phys_addr_t phys,
 	    unsigned int size, int flags);
 
 #else /* !HAVE_BATS */

@@ -339,7 +339,7 @@
 	/*
 	 * Use a BAT for this if possible...
 	 */
-	if (io_bat_index < 2 && is_power_of_2(size)
+	if (io_bat_index < (ppc_bat_count() - 2) && is_power_of_2(size)
 	    && (virt & (size - 1)) == 0 && (phys & (size - 1)) == 0) {
 		setbat(io_bat_index, virt, phys, size, flags);
 		++io_bat_index;

arch/ppc/mm/ppc_mmu.c +21 ~~-15~~

diff -urN linux-2.6.13.3.orig/arch/ppc/mm/ppc_mmu.c linux-2.6.13.3/arch/ppc/mm/ppc_mmu.c
@@ -36,6 +36,7 @@
 #include "mmu_decl.h"
 #include "mem_pieces.h"
 
+
 PTE *Hash, *Hash_end;
 unsigned long Hash_size, Hash_mask;
 unsigned long _SDR1;

@@ -47,13 +48,13 @@
 #else
 	u32	word[2];
 #endif
-} BATS[4][2];			/* 4 pairs of IBAT, DBAT */
+} BATS[PPC_BAT_COUNT][2];			/* 4 pairs of IBAT, DBAT */
 
 struct batrange {		/* stores address ranges mapped by BATs */
 	unsigned long start;
 	unsigned long limit;
-	unsigned long phys;
-} bat_addrs[4];
+	phys_addr_t phys;
+} bat_addrs[PPC_BAT_COUNT];
 
 /*
  * Return PA for this VA if it is mapped by a BAT, or 0

@@ -61,7 +62,7 @@
 unsigned long v_mapped_by_bats(unsigned long va)
 {
 	int b;
-	for (b = 0; b < 4; ++b)
+	for (b = 0; b < PPC_BAT_COUNT; ++b)
 		if (va >= bat_addrs[b].start && va < bat_addrs[b].limit)
 			return bat_addrs[b].phys + (va - bat_addrs[b].start);
 	return 0;

@@ -70,10 +71,10 @@
 /*
  * Return VA for a given PA or 0 if not mapped
  */
-unsigned long p_mapped_by_bats(unsigned long pa)
+unsigned long p_mapped_by_bats(phys_addr_t pa)
 {
 	int b;
-	for (b = 0; b < 4; ++b)
+	for (b = 0; b < PPC_BAT_COUNT; ++b)
 		if (pa >= bat_addrs[b].phys
 	    	    && pa < (bat_addrs[b].limit-bat_addrs[b].start)
 		              +bat_addrs[b].phys)

@@ -87,13 +88,14 @@
 	return 0;
 #else
 	unsigned long tot, bl, done;
-	unsigned long max_size = (256<<20);
+	unsigned long max_size = max_bat_size();
 	unsigned long align;
+	int bat_nbr = ppc_bat_count() - 2;
 
 	if (__map_without_bats)
 		return 0;
 
-	/* Set up BAT2 and if necessary BAT3 to cover RAM. */
+	/* Set up BAT[2|6] and if necessary BAT[3|7] to cover RAM. */
 
 	/* Make sure we don't map a block larger than the
 	   smallest alignment of the physical address. */

@@ -109,16 +111,17 @@
 			break;
 	}
 
-	setbat(2, KERNELBASE, PPC_MEMSTART, bl, _PAGE_RAM);
-	done = (unsigned long)bat_addrs[2].limit - KERNELBASE + 1;
-	if ((done < tot) && !bat_addrs[3].limit) {
-		/* use BAT3 to cover a bit more */
+	setbat(bat_nbr, KERNELBASE, PPC_MEMSTART, bl, _PAGE_RAM);
+	done = (unsigned long)bat_addrs[bat_nbr].limit - KERNELBASE + 1;
+	bat_nbr++;
+	if ((done < tot) && !bat_addrs[bat_nbr].limit) {
+		/* use BAT[3|7] to cover a bit more */
 		tot -= done;
 		for (bl = 128<<10; bl < max_size; bl <<= 1)
 			if (bl * 2 > tot)
 				break;
-		setbat(3, KERNELBASE+done, PPC_MEMSTART+done, bl, _PAGE_RAM);
-		done = (unsigned long)bat_addrs[3].limit - KERNELBASE + 1;
+		setbat(bat_nbr, KERNELBASE+done, PPC_MEMSTART+done, bl, _PAGE_RAM);
+		done = (unsigned long)bat_addrs[bat_nbr].limit - KERNELBASE + 1;
 	}
 
 	return done;

@@ -130,7 +133,7 @@
  * The parameters are not checked; in particular size must be a power
  * of 2 between 128k and 256M.
  */
-void __init setbat(int index, unsigned long virt, unsigned long phys,
+void __init setbat(int index, unsigned long virt, phys_addr_t phys,
 		   unsigned int size, int flags)
 {
 	unsigned int bl;

@@ -148,6 +151,9 @@
 		wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
 				   | _PAGE_COHERENT | _PAGE_GUARDED);
 		wimgxpp |= (flags & _PAGE_RW)? BPP_RW: BPP_RX;
+#ifdef CONFIG_PHYS_64BIT
+		wimgxpp |= ((phys >> 30) & 4) | ((phys >> 24) & 0xe00);
+#endif
 		bat[1].word[0] = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */
 		bat[1].word[1] = phys | wimgxpp;
 #ifndef CONFIG_KGDB /* want user access for breakpoints */

include/asm-ppc/cputable.h +1 -0

diff -urN linux-2.6.13.3.orig/include/asm-ppc/cputable.h linux-2.6.13.3/include/asm-ppc/cputable.h
@@ -89,6 +89,7 @@
 #define CPU_FTR_NEED_COHERENT		0x00020000
 #define CPU_FTR_NO_BTIC			0x00040000
 #define CPU_FTR_BIG_PHYS		0x00080000
+#define CPU_FTR_LARGE_BATS		0x00100000
 
 #ifdef __ASSEMBLY__

include/asm-ppc/mmu.h +19 -0

diff -urN linux-2.6.13.3.orig/include/asm-ppc/mmu.h linux-2.6.13.3/include/asm-ppc/mmu.h
@@ -18,11 +18,30 @@
 #ifndef CONFIG_PHYS_64BIT
 typedef unsigned long phys_addr_t;
 #define PHYS_FMT	"%.8lx"
+#define cpu_has_bigphys() 0
 #else
 typedef unsigned long long phys_addr_t;
 extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t);
 #define PHYS_FMT	"%16Lx"
+#define cpu_has_bigphys() cpu_has_feature(CPU_FTR_BIG_PHYS)
 #endif
+
+#ifdef CONFIG_PPC_LARGE_BATS
+/* We don't allow 4G Bat's because it doesn't fit into size_t */
+#define max_bat_size() (cpu_has_feature(CPU_FTR_LARGE_BATS)?(2<<30):(256<<20))
+#else
+#define max_bat_size() (256<<20)
+#endif
+
+/* High BAT support */
+#ifdef CONFIG_PPC_HIGH_BATS
+#define PPC_BAT_COUNT 8
+#define ppc_bat_count() (cpu_has_feature(CPU_FTR_HAS_HIGH_BATS)?8:4)
+#else
+#define PPC_BAT_COUNT 4
+#define ppc_bat_count() (4)
+#endif
+
 
 /* Default "unsigned long" context */
 typedef unsigned long mm_context_t;

Kumar Gala

2005-10-21 14:28 UTC #2 lore raw

Re: [PATCH][RFT] please use this one

The concept of PPC_HIGH_BATS is already some what handled with CPU_FTR_HAS_HIGH_BATS. I recommend you use this feature instead of introducing another one as well as a compile time option.

- k

Quoted 367 lines · Rupert Eibauer

Hello,

Please try this one. The first one contained a last-second fix which I didn't test if it compiles.

Regards,
Rupert

diff -urN linux-2.6.13.3.orig/arch/ppc/Kconfig linux-2.6.13.3/arch/ppc/Kconfig

arch/ppc/Kconfig Fri Oct 21 05:53:49 2005 renamed from arch/ppc/Kconfig Fri Oct 21 05:42:59 2005 +2 -2

@@ -115,14 +115,28 @@
     default y if E500 && PHYS_64BIT
 
 config PHYS_64BIT
-    bool 'Large physical address support' if E500
-    depends on 44x || E500
+    bool 'Large physical address support' if E500 || 6xx
+    depends on 44x || E500 || 6xx
     default y if 44x
     ---help---
       This option enables kernel support for larger than 32-bit

physical
addresses. This features is not be available on all e500
cores.

If in doubt, say N here.

arch/ppc/Kconfig Fri Oct 21 05:53:49 2005 renamed from arch/ppc/Kconfig Fri Oct 21 05:42:59 2005 +14 -0

+
+config PPC_LARGE_BATS
+    bool 'Extended BAT Block Bize Support' if 6xx
+    depends on 6xx
+    ---help---
+     This option enables kernel support for large BAT
+     addressing mode, which is present on some 7450 chips.
+
+config PPC_HIGH_BATS
+    bool 'High BAT Support' if 6xx
+    depends on 6xx
+    ---help---
+     This option enables kernel support for the 4 additional
+     BATS, which is present on some 7450 chips.
 
 config ALTIVEC
     bool "AltiVec Support"

diff -urN linux-2.6.13.3.orig/arch/ppc/kernel/cpu_setup_6xx.S linux-2.6.13.3/arch/ppc/kernel/cpu_setup_6xx.S
--- linux-2.6.13.3.orig/arch/ppc/kernel/cpu_setup_6xx.S Fri Oct
21 05:49:53 2005
+++ linux-2.6.13.3/arch/ppc/kernel/cpu_setup_6xx.S Fri Oct 21
05:53:49 2005

arch/ppc/Kconfig Fri Oct 21 05:53:49 2005 renamed from arch/ppc/Kconfig Fri Oct 21 05:42:59 2005 +7 -1

@@ -229,13 +229,19 @@
      */
     ori    r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE
     ori    r11,r11,HID0_LRSTK | HID0_BTIC
-    oris    r11,r11,HID0_DPM@h
+    oris    r11,r11,(HID0_DPM | HID0_XAEN)@h
 BEGIN_FTR_SECTION
     xori    r11,r11,HID0_BTIC
 END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC)
 BEGIN_FTR_SECTION
     xoris    r11,r11,HID0_DPM@h    /* disable dynamic power mgmt */
 END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
+BEGIN_FTR_SECTION
+    xoris    r11,r11,HID0_XAEN@h
+END_FTR_SECTION_IFCLR(CPU_FTR_BIG_PHYS)
+BEGIN_FTR_SECTION
+    ori    r11,r11,HID0_XBSEN
+END_FTR_SECTION_IFSET(CPU_FTR_LARGE_BATS)
 
     /* All of the bits we have to clear....
      */

diff -urN linux-2.6.13.3.orig/arch/ppc/kernel/cputable.c linux-2.6.13.3/arch/ppc/kernel/cputable.c
--- linux-2.6.13.3.orig/arch/ppc/kernel/cputable.c Fri Oct 21
05:49:53 2005
+++ linux-2.6.13.3/arch/ppc/kernel/cputable.c Fri Oct 21
05:53:49 2005

arch/ppc/Kconfig Fri Oct 21 05:53:49 2005 renamed from arch/ppc/Kconfig Fri Oct 21 05:42:59 2005 +13 -0

@@ -62,6 +62,18 @@
 #define PPC_FEATURE_SPE_COMP           0
 #endif
 
+#ifdef CONFIG_PPC_LARGE_BATS
+#define CPU_FTR_LARGE_BATS_COMP        CPU_FTR_LARGE_BATS
+#else
+#define CPU_FTR_LARGE_BATS_COMP        0
+#endif
+
+#ifndef CONFIG_PHYS_64BIT
+#define CPU_FTR_BIG_PHYS_COMP        CPU_FTR_BIG_PHYS
+#else
+#define CPU_FTR_BIG_PHYS_COMP        0
+#endif
+
 /* We need to mark all pages as being coherent if we're SMP or we
  * have a 74[45]x and an MPC107 host bridge.
  */

@@ -428,6 +440,7 @@
             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
             CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
             CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+            CPU_FTR_BIG_PHYS_COMP | CPU_FTR_LARGE_BATS_COMP |
             CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
         .cpu_user_features    = COMMON_PPC |  
 PPC_FEATURE_ALTIVEC_COMP,

.icache_bsize = 32,

arch/ppc/Kconfig Fri Oct 21 05:53:49 2005 renamed from arch/ppc/Kconfig Fri Oct 21 05:42:59 2005 +1 -0

@@ -445,6 +458,7 @@
             CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
             CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
+            CPU_FTR_BIG_PHYS_COMP | CPU_FTR_LARGE_BATS_COMP |
             CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
         .cpu_user_features    = COMMON_PPC |  
 PPC_FEATURE_ALTIVEC_COMP,

.icache_bsize = 32,

arch/ppc/Kconfig Fri Oct 21 05:53:49 2005 renamed from arch/ppc/Kconfig Fri Oct 21 05:42:59 2005 +1 -0

@@ -462,6 +476,7 @@
             CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
             CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+            CPU_FTR_BIG_PHYS_COMP | CPU_FTR_LARGE_BATS_COMP |
             CPU_FTR_NEED_COHERENT,
         .cpu_user_features    = COMMON_PPC |  
 PPC_FEATURE_ALTIVEC_COMP,

.icache_bsize = 32,

arch/ppc/Kconfig Fri Oct 21 05:53:49 2005 renamed from arch/ppc/Kconfig Fri Oct 21 05:42:59 2005 +1 -0

@@ -478,6 +493,7 @@
             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
             CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
             CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+            CPU_FTR_BIG_PHYS_COMP | CPU_FTR_LARGE_BATS_COMP |
             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
             CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
         .cpu_user_features    = COMMON_PPC |

PPC_FEATURE_ALTIVEC_COMP,

arch/ppc/Kconfig Fri Oct 21 05:53:49 2005 renamed from arch/ppc/Kconfig Fri Oct 21 05:42:59 2005 +1 -0

@@ -496,6 +512,7 @@
             CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
             CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+            CPU_FTR_BIG_PHYS_COMP | CPU_FTR_LARGE_BATS_COMP |
             CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
         .cpu_user_features    = COMMON_PPC |  
 PPC_FEATURE_ALTIVEC_COMP,

.icache_bsize = 32,

arch/ppc/Kconfig Fri Oct 21 05:53:49 2005 renamed from arch/ppc/Kconfig Fri Oct 21 05:42:59 2005 +1 -0

@@ -513,6 +530,7 @@
             CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
             CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+            CPU_FTR_BIG_PHYS_COMP | CPU_FTR_LARGE_BATS_COMP |
             CPU_FTR_NEED_COHERENT,
         .cpu_user_features    = COMMON_PPC |  
 PPC_FEATURE_ALTIVEC_COMP,

.icache_bsize = 32,

arch/ppc/Kconfig Fri Oct 21 05:53:49 2005 renamed from arch/ppc/Kconfig Fri Oct 21 05:42:59 2005 +1 -0

@@ -529,6 +547,7 @@
             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
             CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
             CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
+            CPU_FTR_BIG_PHYS_COMP | CPU_FTR_LARGE_BATS_COMP |
             CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
         .cpu_user_features    = COMMON_PPC |  
 PPC_FEATURE_ALTIVEC_COMP,

.icache_bsize = 32,
diff -urN linux-2.6.13.3.orig/arch/ppc/kernel/head.S linux-2.6.13.3/arch/ppc/kernel/head.S
--- linux-2.6.13.3.orig/arch/ppc/kernel/head.S Fri Oct 21
05:49:53 2005
+++ linux-2.6.13.3/arch/ppc/kernel/head.S Fri Oct 21 05:53:49 2005

arch/ppc/Kconfig Fri Oct 21 05:53:49 2005 renamed from arch/ppc/Kconfig Fri Oct 21 05:42:59 2005 +8 -0

@@ -1165,6 +1165,14 @@
     LOAD_BAT(1,r3,r4,r5)
     LOAD_BAT(2,r3,r4,r5)
     LOAD_BAT(3,r3,r4,r5)
+#ifdef CONFIG_PPC_HIGH_BATS
+BEGIN_FTR_SECTION
+    LOAD_BAT(4,r3,r4,r5)
+    LOAD_BAT(5,r3,r4,r5)
+    LOAD_BAT(6,r3,r4,r5)
+    LOAD_BAT(7,r3,r4,r5)
+END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
+#endif /* CONFIG_PPC_HIGH_BATS */
 #endif /* CONFIG_POWER4 */
     blr

diff -urN linux-2.6.13.3.orig/arch/ppc/mm/pgtable.c linux-2.6.13.3/arch/ppc/mm/pgtable.c
--- linux-2.6.13.3.orig/arch/ppc/mm/pgtable.c Fri Oct 21
05:49:53 2005
+++ linux-2.6.13.3/arch/ppc/mm/pgtable.c Fri Oct 21 05:53:49 2005

arch/ppc/Kconfig Fri Oct 21 05:53:49 2005 renamed from arch/ppc/Kconfig Fri Oct 21 05:42:59 2005 +3 -3

@@ -55,8 +55,8 @@
 
 #ifdef HAVE_BATS
 extern unsigned long v_mapped_by_bats(unsigned long va);
-extern unsigned long p_mapped_by_bats(unsigned long pa);
-void setbat(int index, unsigned long virt, unsigned long phys,
+extern unsigned long p_mapped_by_bats(phys_addr_t pa);
+void setbat(int index, unsigned long virt, phys_addr_t phys,
         unsigned int size, int flags);
 
 #else /* !HAVE_BATS */

@@ -339,7 +339,7 @@
     /*
      * Use a BAT for this if possible...
      */
-    if (io_bat_index < 2 && is_power_of_2(size)
+    if (io_bat_index < (ppc_bat_count() - 2) && is_power_of_2(size)
         && (virt & (size - 1)) == 0 && (phys & (size - 1)) == 0) {
         setbat(io_bat_index, virt, phys, size, flags);
         ++io_bat_index;

diff -urN linux-2.6.13.3.orig/arch/ppc/mm/ppc_mmu.c linux-2.6.13.3/arch/ppc/mm/ppc_mmu.c
--- linux-2.6.13.3.orig/arch/ppc/mm/ppc_mmu.c Fri Oct 21
05:49:53 2005
+++ linux-2.6.13.3/arch/ppc/mm/ppc_mmu.c Fri Oct 21 05:53:49 2005

arch/ppc/Kconfig Fri Oct 21 05:53:49 2005 renamed from arch/ppc/Kconfig Fri Oct 21 05:42:59 2005 +17 ~~-14~~

@@ -36,6 +36,7 @@
 #include "mmu_decl.h"
 #include "mem_pieces.h"
 
+
 PTE *Hash, *Hash_end;
 unsigned long Hash_size, Hash_mask;
 unsigned long _SDR1;

@@ -47,13 +48,13 @@
 #else
     u32    word[2];
 #endif
-} BATS[4][2];            /* 4 pairs of IBAT, DBAT */
+} BATS[PPC_BAT_COUNT][2];            /* 4 pairs of IBAT, DBAT */
 
 struct batrange {        /* stores address ranges mapped by BATs */
     unsigned long start;
     unsigned long limit;
-    unsigned long phys;
-} bat_addrs[4];
+    phys_addr_t phys;
+} bat_addrs[PPC_BAT_COUNT];
 
 /*
  * Return PA for this VA if it is mapped by a BAT, or 0

@@ -61,7 +62,7 @@
 unsigned long v_mapped_by_bats(unsigned long va)
 {
     int b;
-    for (b = 0; b < 4; ++b)
+    for (b = 0; b < PPC_BAT_COUNT; ++b)
         if (va >= bat_addrs[b].start && va < bat_addrs[b].limit)
             return bat_addrs[b].phys + (va - bat_addrs[b].start);
     return 0;

@@ -70,10 +71,10 @@
 /*
  * Return VA for a given PA or 0 if not mapped
  */
-unsigned long p_mapped_by_bats(unsigned long pa)
+unsigned long p_mapped_by_bats(phys_addr_t pa)
 {
     int b;
-    for (b = 0; b < 4; ++b)
+    for (b = 0; b < PPC_BAT_COUNT; ++b)
         if (pa >= bat_addrs[b].phys
                 && pa < (bat_addrs[b].limit-bat_addrs[b].start)
                       +bat_addrs[b].phys)

@@ -87,13 +88,14 @@
     return 0;
 #else
     unsigned long tot, bl, done;
-    unsigned long max_size = (256<<20);
+    unsigned long max_size = max_bat_size();
     unsigned long align;
+    int bat_nbr = ppc_bat_count() - 2;
 
     if (__map_without_bats)
         return 0;
 
-    /* Set up BAT2 and if necessary BAT3 to cover RAM. */
+    /* Set up BAT[2|6] and if necessary BAT[3|7] to cover RAM. */
 
     /* Make sure we don't map a block larger than the
        smallest alignment of the physical address. */

@@ -109,16 +111,17 @@
             break;
     }
 
-    setbat(2, KERNELBASE, PPC_MEMSTART, bl, _PAGE_RAM);
-    done = (unsigned long)bat_addrs[2].limit - KERNELBASE + 1;
-    if ((done < tot) && !bat_addrs[3].limit) {
-        /* use BAT3 to cover a bit more */
+    setbat(bat_nbr, KERNELBASE, PPC_MEMSTART, bl, _PAGE_RAM);
+    done = (unsigned long)bat_addrs[bat_nbr].limit - KERNELBASE + 1;
+    bat_nbr++;
+    if ((done < tot) && !bat_addrs[bat_nbr].limit) {
+        /* use BAT[3|7] to cover a bit more */
         tot -= done;
         for (bl = 128<<10; bl < max_size; bl <<= 1)
             if (bl * 2 > tot)
                 break;
-        setbat(3, KERNELBASE+done, PPC_MEMSTART+done, bl, _PAGE_RAM);
-        done = (unsigned long)bat_addrs[3].limit - KERNELBASE + 1;
+        setbat(bat_nbr, KERNELBASE+done, PPC_MEMSTART+done, bl,  
 _PAGE_RAM);
+        done = (unsigned long)bat_addrs[bat_nbr].limit -  
 KERNELBASE + 1;
     }

     return done;

arch/ppc/Kconfig Fri Oct 21 05:53:49 2005 renamed from arch/ppc/Kconfig Fri Oct 21 05:42:59 2005 +4 -1

@@ -130,7 +133,7 @@
  * The parameters are not checked; in particular size must be a power
  * of 2 between 128k and 256M.
  */
-void __init setbat(int index, unsigned long virt, unsigned long phys,
+void __init setbat(int index, unsigned long virt, phys_addr_t phys,
            unsigned int size, int flags)
 {
     unsigned int bl;

@@ -148,6 +151,9 @@
         wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
                    | _PAGE_COHERENT | _PAGE_GUARDED);
         wimgxpp |= (flags & _PAGE_RW)? BPP_RW: BPP_RX;
+#ifdef CONFIG_PHYS_64BIT
+        wimgxpp |= ((phys >> 30) & 4) | ((phys >> 24) & 0xe00);
+#endif
         bat[1].word[0] = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */
         bat[1].word[1] = phys | wimgxpp;
 #ifndef CONFIG_KGDB /* want user access for breakpoints */

diff -urN linux-2.6.13.3.orig/include/asm-ppc/cputable.h linux-2.6.13.3/include/asm-ppc/cputable.h
--- linux-2.6.13.3.orig/include/asm-ppc/cputable.h Thu Jun 30
01:00:53 2005
+++ linux-2.6.13.3/include/asm-ppc/cputable.h Fri Oct 21
05:53:49 2005

arch/ppc/Kconfig Fri Oct 21 05:53:49 2005 renamed from arch/ppc/Kconfig Fri Oct 21 05:42:59 2005 +1 -0

@@ -89,6 +89,7 @@
 #define CPU_FTR_NEED_COHERENT        0x00020000
 #define CPU_FTR_NO_BTIC            0x00040000
 #define CPU_FTR_BIG_PHYS        0x00080000
+#define CPU_FTR_LARGE_BATS        0x00100000
 
 #ifdef __ASSEMBLY__

diff -urN linux-2.6.13.3.orig/include/asm-ppc/mmu.h linux-2.6.13.3/include/asm-ppc/mmu.h
--- linux-2.6.13.3.orig/include/asm-ppc/mmu.h Fri Oct 21
05:44:49 2005
+++ linux-2.6.13.3/include/asm-ppc/mmu.h Fri Oct 21 05:53:49 2005

arch/ppc/Kconfig Fri Oct 21 05:53:49 2005 renamed from arch/ppc/Kconfig Fri Oct 21 05:42:59 2005 +19 -0

@@ -18,11 +18,30 @@
 #ifndef CONFIG_PHYS_64BIT
 typedef unsigned long phys_addr_t;
 #define PHYS_FMT    "%.8lx"
+#define cpu_has_bigphys() 0
 #else
 typedef unsigned long long phys_addr_t;
 extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t);
 #define PHYS_FMT    "%16Lx"
+#define cpu_has_bigphys() cpu_has_feature(CPU_FTR_BIG_PHYS)
 #endif
+
+#ifdef CONFIG_PPC_LARGE_BATS
+/* We don't allow 4G Bat's because it doesn't fit into size_t */
+#define max_bat_size() (cpu_has_feature(CPU_FTR_LARGE_BATS)? 
 (2<<30):(256<<20))
+#else
+#define max_bat_size() (256<<20)
+#endif
+
+/* High BAT support */
+#ifdef CONFIG_PPC_HIGH_BATS
+#define PPC_BAT_COUNT 8
+#define ppc_bat_count() (cpu_has_feature(CPU_FTR_HAS_HIGH_BATS)?8:4)
+#else
+#define PPC_BAT_COUNT 4
+#define ppc_bat_count() (4)
+#endif
+
 
 /* Default "unsigned long" context */

typedef unsigned long mm_context_t;
_______________________________________________
Linuxppc-dev mailing list
[email protected]
https://ozlabs.org/mailman/listinfo/linuxppc-dev

Rupert Eibauer

author

2005-10-21 14:55 UTC #3 lore raw

Re: [PATCH][RFT] please use this one

Quoted 3 lines · Kumar Gala

The concept of PPC_HIGH_BATS is already some what handled with CPU_FTR_HAS_HIGH_BATS. I recommend you use this feature instead of introducing another one as well as a compile time option.

CPU_FTR_HAS_HIGH_BATS only clears the high bats, but does not attempt to use them. My patch will use them.

Rupert

Quoted 3 lines

- k

Kumar Gala

2005-10-21 15:22 UTC #4 lore raw

Re: [PATCH][RFT] please use this one

Quoted 9 lines · Rupert Eibauer

Quoted 4 lines · Kumar Gala
The concept of PPC_HIGH_BATS is already some what handled with CPU_FTR_HAS_HIGH_BATS. I recommend you use this feature instead of introducing another one as well as a compile time option.
CPU_FTR_HAS_HIGH_BATS only clears the high bats, but does not attempt to use them. My patch will use them.

I understand, I'm suggesting you expand CPU_FTR_HAS_HIGH_BATS to include your additional functionality.

- kumar

Rupert Eibauer

author

2005-10-21 18:28 UTC #5 lore raw

Re: [PATCH][RFT] please use this one

Quoted 10 lines · Kumar Gala

Quoted 7 lines · Rupert Eibauer
Quoted 4 lines · Kumar Gala
The concept of PPC_HIGH_BATS is already some what handled with CPU_FTR_HAS_HIGH_BATS. I recommend you use this feature instead of introducing another one as well as a compile time option.

Quoted 5 lines

Quoted 2 lines
CPU_FTR_HAS_HIGH_BATS only clears the high bats, but does not attempt to use them. My patch will use them.
I understand, I'm suggesting you expand CPU_FTR_HAS_HIGH_BATS to include your additional functionality.

How do you mean that exactly?

Do you mean making the feature always-on (not selectable in Kconfig)? Having CONFIG_PPC_LARGE_BATS and CONFIG_HIGH_PATS always-on would be ok for me, but for PHYS_64BIT should be left up to the platform to decide if it should be presented to the user or not.

Do you think the other two features, CPU_FTR_BIG_PHYS and CPU_FTR_LARGE_BATS should be merged into one bit? They could for now, because there is no processor supporting only one of them.

Rupert

Quoted 2 lines

- kumar

Kumar Gala

2005-10-21 18:33 UTC #6 lore raw

Re: [PATCH][RFT] please use this one

Quoted 23 lines · Rupert Eibauer

Quoted 13 lines · Kumar Gala
Quoted 9 lines · Rupert Eibauer
Quoted 5 lines · Kumar Gala
The concept of PPC_HIGH_BATS is already some what handled with CPU_FTR_HAS_HIGH_BATS. I recommend you use this feature instead of introducing another one as well as a compile time option.
Quoted 7 lines
Quoted 3 lines
CPU_FTR_HAS_HIGH_BATS only clears the high bats, but does not attempt to use them. My patch will use them.
I understand, I'm suggesting you expand CPU_FTR_HAS_HIGH_BATS to include your additional functionality.

Quoted 6 lines

How do you mean that exactly?
Do you mean making the feature always-on (not selectable in Kconfig)? Having CONFIG_PPC_LARGE_BATS and CONFIG_HIGH_PATS always-on would be ok for me, but for PHYS_64BIT should be left up to the platform to decide if it should be presented to the user or not.

Yes, I think just making support for BATS 4-7 always on and use CONFIG_FTR_HAS_HIGH_BATS for any runtime fixup.

Quoted 3 lines

Do you think the other two features, CPU_FTR_BIG_PHYS and CPU_FTR_LARGE_BATS should be merged into one bit? They could for now, because there is no processor supporting only one of them.

Yes, this should still be a config option. Merging CPU_FTR_LARGE_BATS into CPU_FTR_BIG_PHYS should be ok.

- kumar