Skip to contentSkip to conversation

AMD Geode GX/LX Support (Refreshed)

PATCH Applied Jordan Crouse 3 participants 12 messages Oct 28, 2005 – Nov 9, 2005 1 message not in the archive

Subsystems (3)
lore
Share & tools
lore

A message that is not in the archive (sent off-list or not yet received): LYRIS-4270-74122-2005.10.28-09.38.17--jordan.crouse#[email protected]

#1 lore raw

PATCH 1/6 AMD Geode GX/LX Support (Refreshed)

This is the base GX/LX support patch. Prior changelog:

* fixed up the MGEODEGX1 cache line size to the correct value.
* Removed GEODE_LX restrictions from IOAPIC and HIGHMEM (Alan Cox and others)
* Removed GEODE_LX define from the 3DNOW config option pending conclusive benchmark results that it increases performance (Alan Cox)
* Fix up the GX1/GX cpu init function so that it is cleaner and more correct. If anybody gets a NSC branded GX1 processor, it should jump into the init_cyrix and do the right thing. (Alan Cox)
* Updated the MAINTAINERS information (Adrian Bunk)

MAINTAINERS                  |    7 +++++++
arch/i386/Kconfig            |   12 +++++++++---
arch/i386/kernel/cpu/amd.c   |    7 +++++++
arch/i386/kernel/cpu/cyrix.c |   32 +++++++++++++++++++++++++++++++-
include/asm-i386/module.h    |    4 +++-
include/linux/pci_ids.h      |   10 ++++++++++
6 files changed, 67 insertions(+), 5 deletions(-)
arch/i386/Kconfig +9 -3
Index: linux-2.6.14/arch/i386/Kconfig
===================================================================
@@ -191,6 +191,7 @@ config M386
 	  - "Winchip-2" for IDT Winchip 2.
 	  - "Winchip-2A" for IDT Winchips with 3dNow! capabilities.
 	  - "GeodeGX1" for Geode GX1 (Cyrix MediaGX).
+	  - "Geode GX/LX" For AMD Geode GX and LX processors.
 	  - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3.
 	  - "VIA C3-2 for VIA C3-2 "Nehemiah" (model 9 and above).
 
@@ -323,6 +324,11 @@ config MGEODEGX1
 	help
 	  Select this for a Geode GX1 (Cyrix MediaGX) chip.
 
+config MGEODE_LX
+       bool "Geode GX/LX"
+       help
+         Select this for AMD Geode GX and LX processors.
+
 config MCYRIXIII
 	bool "CyrixIII/VIA-C3"
 	help
@@ -372,8 +378,8 @@ config X86_XADD
 config X86_L1_CACHE_SHIFT
 	int
 	default "7" if MPENTIUM4 || X86_GENERIC
-	default "4" if X86_ELAN || M486 || M386
-	default "5" if MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODEGX1
+	default "4" if X86_ELAN || M486 || M386 || MGEODEGX1
+	default "5" if MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
 	default "6" if MK7 || MK8 || MPENTIUMM
 
 config RWSEM_GENERIC_SPINLOCK
@@ -437,7 +443,7 @@ config X86_INTEL_USERCOPY
 
 config X86_USE_PPRO_CHECKSUM
 	bool
-	depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MEFFICEON
+	depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MEFFICEON || MGEODE_LX
 	default y
 
 config X86_USE_3DNOW
arch/i386/kernel/cpu/amd.c +7 -0
Index: linux-2.6.14/arch/i386/kernel/cpu/amd.c
===================================================================
@@ -161,6 +161,13 @@ static void __init init_amd(struct cpuin
 					set_bit(X86_FEATURE_K6_MTRR, c->x86_capability);
 				break;
 			}
+
+			if ( c->x86_model == 10 ) {
+				/* AMD Geode LX is model 10 */
+				/* placeholder for any needed mods */
+				break;
+			}
+
 			break;
 
 		case 6: /* An Athlon/Duron */
include/linux/pci_ids.h +10 -0
Index: linux-2.6.14/include/linux/pci_ids.h
===================================================================
@@ -405,6 +405,13 @@
 #define PCI_DEVICE_ID_NS_SC1100_XBUS	0x0515
 #define PCI_DEVICE_ID_NS_87410		0xd001
 
+#define PCI_DEVICE_ID_NS_CS5535_HOST_BRIDGE  0x0028
+#define PCI_DEVICE_ID_NS_CS5535_ISA_BRIDGE   0x002b
+#define PCI_DEVICE_ID_NS_CS5535_IDE          0x002d
+#define PCI_DEVICE_ID_NS_CS5535_AUDIO        0x002e
+#define PCI_DEVICE_ID_NS_CS5535_USB          0x002f
+#define PCI_DEVICE_ID_NS_CS5535_VIDEO        0x0030
+
 #define PCI_VENDOR_ID_TSENG		0x100c
 #define PCI_DEVICE_ID_TSENG_W32P_2	0x3202
 #define PCI_DEVICE_ID_TSENG_W32P_b	0x3205
@@ -536,6 +543,9 @@
 #define PCI_DEVICE_ID_AMD_8151_0	0x7454
 #define PCI_DEVICE_ID_AMD_8131_APIC     0x7450
 
+#define PCI_DEVICE_ID_AMD_LX_VIDEO  0x2081
+#define PCI_DEVICE_ID_AMD_LX_AES    0x2082
+
 #define PCI_VENDOR_ID_TRIDENT		0x1023
 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX	0x2000
 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX	0x2001
MAINTAINERS +7 -0
Index: linux-2.6.14/MAINTAINERS
===================================================================
@@ -252,6 +252,13 @@ P:	Ivan Kokshaysky
 M:	[email protected]
 S:	Maintained for 2.4; PCI support for 2.6.
 
+AMD GEODE PROCESSOR/CHIPSET SUPPORT
+P:      Jordan Crouse
+M:      [email protected]
+L:	[email protected]
+W:	http://www.amd.com/us-en/ConnectivitySolutions/TechnicalResources/0,,50_2334_2452_11363,00.html
+S:	Supported
+
 APM DRIVER
 P:	Stephen Rothwell
 M:	[email protected]
arch/i386/kernel/cpu/cyrix.c +31 -1
Index: linux-2.6.14/arch/i386/kernel/cpu/cyrix.c
===================================================================
@@ -342,6 +342,36 @@ static void __init init_cyrix(struct cpu
 	return;
 }
 
+
+/* This function handles National Semiconductor branded processors */
+
+static void __init init_nsc(struct cpuinfo_x86 *c)
+{
+	int r;
+
+	/* There may be GX1 processors in the wild that are branded
+	 * NSC and not Cyrix.
+	 *
+	 * This function only handles the GX processor, and kicks every
+	 * thing else to the Cyrix init function above - that should
+	 * cover any processors that might have been branded differently
+	 * after NSC aquired Cyrix.
+	 *
+	 * If this breaks your GX1 horribly, please e-mail
+	 * [email protected] to tell us.
+	 */
+
+	/* Handle the GX (Formally known as the GX2) */
+
+	if ((c->x86 == 5) && (c->x86_model == 5)) {
+		r = get_model_name(c);
+		display_cacheinfo(c);
+	}
+	else
+		init_cyrix(c);
+}
+
+
 /*
  * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
  * by the fact that they preserve the flags across the division of 5/2.
@@ -422,7 +452,7 @@ int __init cyrix_init_cpu(void)
 static struct cpu_dev nsc_cpu_dev __initdata = {
 	.c_vendor	= "NSC",
 	.c_ident 	= { "Geode by NSC" },
-	.c_init		= init_cyrix,
+	.c_init		= init_nsc,
 	.c_identify	= generic_identify,
 };
 
include/asm-i386/module.h +3 -1
Index: linux-2.6.14/include/asm-i386/module.h
===================================================================
@@ -52,8 +52,10 @@ struct mod_arch_specific
 #define MODULE_PROC_FAMILY "CYRIXIII "
 #elif defined CONFIG_MVIAC3_2
 #define MODULE_PROC_FAMILY "VIAC3-2 "
-#elif CONFIG_MGEODEGX1
+#elif defined CONFIG_MGEODEGX1
 #define MODULE_PROC_FAMILY "GEODEGX1 "
+#elif defined CONFIG_MGEODE_LX
+#define MODULE_PROC_FAMILY "GEODE "
 #else
 #error unknown processor family
 #endif
#2 lore raw

6_INTEL_USERCOPY

arch/i386/Kconfig config X86_INTEL_USERCOPY · line 447

Quoted 6 lines

config X86_USE_PPRO_CHECKSUM

arch/i386/Kconfig +1 -1
 	bool
-	depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MEFFICEON
+	depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MEFFICEON || MGEODE_LX
 	default y

Does this mean you've now done actual performance analysis on whether this is a good idea for Geode GX/LX ?

Quoted 1 line

config X86_USE_3DNOW

#3 lore raw
Quoted 2 lines

Does this mean you've now done actual performance analysis on whether this is a good idea for Geode GX/LX ?

I'm fairly sure that the ppro checksum is faster, but you're exactly right, we should publish some numbers. Mia culpa.

Jordan

Signature · 4 lines
Jordan Crouse
Senior Linux Engineer
AMD - Personal Connectivity Solutions Group
<www.amd.com/embeddedprocessors>
#4 lore raw
In reply to Alan Cox
Quoted 3 lines
Quoted 1 line

config X86_USE_PPRO_CHECKSUM

Does this mean you've now done actual performance analysis on whether this is a good idea for Geode GX/LX ?

Ok - here is some data that should put your mind at ease. I pulled the checksum functions from the kernel, stuck them in userland, and ran each one N times at a variety of byte sizes (where N=10,000), took the start and stop times with gettimeofday(), and added it all up. The results for the Geode LX platfrom are below.

I think the data shows that the ppro checksum is indeed useful on the Geode LX platform (and the GX should have similar results, since the pipelines are pretty close). Unless I made a really boneheaded mistake in my app, I think we should leave X86_USE_PPRO_CHECKSUM enabled for Geode GX/LX.

Jordan

Starting non-ppro test....
Bytes Time Avg (usec/run)
----------------------------

16      2029    0.202900
32      1666    0.166600
64      2548    0.254800
128     3429    0.342900
256     5268    0.526800
512     8781    0.878100
1024    16031   1.603100
2048    30548   3.054800
4096    59265   5.926500

Total time: 129565

Starting ppro test....
Bytes Time Avg (usec/run)
----------------------------

16      1579    0.157900
32      1655    0.165500
64      1841    0.184100
128     2721    0.272100
256     3582    0.358200
512     5264    0.526400
1024    8900    0.890000
2048    15919   1.591900
4096    29369   2.936900

Total time: 70830

#5 lore raw
Quoted 2 lines · Jordan Crouse

in my app, I think we should leave X86_USE_PPRO_CHECKSUM enabled for Geode GX/LX.

Definitely.

#6 lore raw

PATCH 2/6 AMD Geode GX/LX Support (Refreshed)

In reply to a message not in the archive

This is a simple patch that fixes console APM blanking on the GX/LX platforms with BIOSes that still support APM.

apm.c | 27 ++++++++++++++-------------

1 file changed, 14 insertions(+), 13 deletions(-)
arch/i386/kernel/apm.c +14 -13
Index: linux-2.6.14/arch/i386/kernel/apm.c
===================================================================
@@ -1054,22 +1054,23 @@ static int apm_engage_power_management(u
  
 static int apm_console_blank(int blank)
 {
-	int	error;
-	u_short	state;
+	int error, i;
+	u_short state;
+	u_short dev[3] = { 0x100, 0x1FF, 0x101 };
 
 	state = blank ? APM_STATE_STANDBY : APM_STATE_READY;
-	/* Blank the first display device */
-	error = set_power_state(0x100, state);
-	if ((error != APM_SUCCESS) && (error != APM_NO_ERROR)) {
-		/* try to blank them all instead */
-		error = set_power_state(0x1ff, state);
-		if ((error != APM_SUCCESS) && (error != APM_NO_ERROR))
-			/* try to blank device one instead */
-			error = set_power_state(0x101, state);
+
+	for (i = 0; i < 3; i++) {
+		error = set_power_state(dev[i], state);
+
+		if ((error == APM_SUCCESS) || (error == APM_NO_ERROR))
+			return 1;
+
+		if (error == APM_NOT_ENGAGED)
+			break;
 	}
-	if ((error == APM_SUCCESS) || (error == APM_NO_ERROR))
-		return 1;
-	if (error == APM_NOT_ENGAGED) {
+
+	if (error == APM_NOT_ENGAGED && state != APM_STATE_READY) {
 		static int tried;
 		int eng_error;
 		if (tried++ == 0) {
#7 lore raw

PATCH 3/6 AMD Geode GX/LX Support (Refreshed)

In reply to a message not in the archive

The 5535 has a muxed serial port that can either be used to drive GPIO pins or a second 16550 UART. This code enables that UART via a command line option.
This is most often used with a dongle attached to the VGA port to provide a a serial port on boards with no dedicated serial goesouta.

Kconfig       |   11 +++++++
Makefile      |    1
cs5535_uart.c |   83 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 95 insertions(+)
drivers/serial/Kconfig +11 -0
Index: linux-2.6.14/drivers/serial/Kconfig
===================================================================
@@ -608,6 +608,17 @@ config SERIAL_AU1X00_CONSOLE
 	  If you have an Alchemy AU1X00 processor (MIPS based) and you want
 	  to use a console on a serial port, say Y.  Otherwise, say N.
 
+config SERIAL_GEODE_UART2
+	bool "Enable AMD CS5535 UART2 as a serial port"
+	depends on MGEODE_LX
+	default y
+	select SERIAL_CORE
+	help
+	  Select this to allow the user to select the secondary CS5535 UART
+	  as a 16550 serial port instead of the default DDC interface. The
+	  UART2 can be selected by specifying geodeuart2 on the command
+	  line.
+
 config SERIAL_CORE
 	tristate
 
drivers/serial/Makefile +1 -0
Index: linux-2.6.14/drivers/serial/Makefile
===================================================================
@@ -56,3 +56,4 @@ obj-$(CONFIG_SERIAL_JSM) += jsm/
 obj-$(CONFIG_SERIAL_TXX9) += serial_txx9.o
 obj-$(CONFIG_SERIAL_VR41XX) += vr41xx_siu.o
 obj-$(CONFIG_SERIAL_SGI_IOC4) += ioc4_serial.o
+obj-$(CONFIG_SERIAL_GEODE_UART2) += cs5535_uart.o
drivers/serial/cs5535_uart.c new file +83 -0

83 lines not on this page · raw message

#8 lore raw

PATCH 4/6 AMD Geode GX/LX Support (Refreshed)

In reply to a message not in the archive

This is a refresh of Jaya Kumar's patch for the CS5535 IDE on the linux-ide list for 2.6.16 - All glory should go to him, I'm just including it here to complete the set.

Kconfig      |    9 +
pci/Makefile |    1
pci/cs5535.c |  305 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 315 insertions(+)
drivers/ide/Kconfig +9 -0
Index: linux-2.6.14/drivers/ide/Kconfig
===================================================================
@@ -539,6 +539,15 @@ config BLK_DEV_CS5530
 
 	  It is safe to say Y to this question.
 
+config BLK_DEV_CS5535
+	tristate "AMD CS5535 chipset support"
+	depends on X86 && !X86_64
+	help
+	  Include support for UDMA on the NSC/AMD CS5535 companion chipset.
+	  This will automatically be detected and configured if found.
+
+	  It is safe to say Y to this question.
+
 config BLK_DEV_HPT34X
 	tristate "HPT34X chipset support"
 	help
drivers/ide/pci/cs5535.c new file +305 -0

305 lines not on this page · raw message

drivers/ide/pci/Makefile +1 -0
Index: linux-2.6.14/drivers/ide/pci/Makefile
===================================================================
@@ -6,6 +6,7 @@ obj-$(CONFIG_BLK_DEV_ATIIXP)		+= atiixp.
 obj-$(CONFIG_BLK_DEV_CMD64X)		+= cmd64x.o
 obj-$(CONFIG_BLK_DEV_CS5520)		+= cs5520.o
 obj-$(CONFIG_BLK_DEV_CS5530)		+= cs5530.o
+obj-$(CONFIG_BLK_DEV_CS5535)		+= cs5535.o
 obj-$(CONFIG_BLK_DEV_SC1200)		+= sc1200.o
 obj-$(CONFIG_BLK_DEV_CY82C693)		+= cy82c693.o
 obj-$(CONFIG_BLK_DEV_HPT34X)		+= hpt34x.o
Signature · 4 lines
Jordan Crouse
Senior Linux Engineer
AMD - Personal Connectivity Solutions Group
<www.amd.com/embeddedprocessors>
#10 lore raw

PATCH 5/6 AMD Geode GX/LX Support (Refreshed)

In reply to a message not in the archive

Patch for the AMD LX RNG device. Allow me to say at this point that even though I'm patching the current file, I am in favor of the recent RNG rewrite that was proposed a few weeks ago. Changelog:

* Remove defines, style cleanups (Vladis Kletnieks, Alan Cox, Andi Kleen)
* Replace pointer derefrences with readl (Vladis, Alan and Andi again)
* Add asserts to protect against NULL dereferences (Vladis)

hw_random.c | 66
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-

1 file changed, 65 insertions(+), 1 deletion(-)
drivers/char/hw_random.c +65 -1
Index: linux-2.6.14/drivers/char/hw_random.c
===================================================================
@@ -1,4 +1,9 @@
 /*
+        Added support for the AMD Geode LX RNG
+	(c) Copyright 2004-2005 Advanced Micro Devices, Inc.
+
+	derived from
+
  	Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
 	(c) Copyright 2003 Red Hat Inc <[email protected]>
  
@@ -95,6 +100,11 @@ static unsigned int via_data_present (vo
 static u32 via_data_read (void);
 #endif
 
+static int __init geode_init(struct pci_dev *dev);
+static void geode_cleanup(void);
+static unsigned int geode_data_present (void);
+static u32 geode_data_read (void);
+
 struct rng_operations {
 	int (*init) (struct pci_dev *dev);
 	void (*cleanup) (void);
@@ -122,6 +132,7 @@ enum {
 	rng_hw_intel,
 	rng_hw_amd,
 	rng_hw_via,
+	rng_hw_geode,
 };
 
 static struct rng_operations rng_vendor_ops[] = {
@@ -139,6 +150,9 @@ static struct rng_operations rng_vendor_
 	/* rng_hw_via */
 	{ via_init, via_cleanup, via_data_present, via_data_read, 1 },
 #endif
+
+	/* rng_hw_geode */
+	{ geode_init, geode_cleanup, geode_data_present, geode_data_read, 4 }
 };
 
 /*
@@ -159,6 +173,9 @@ static struct pci_device_id rng_pci_tbl[
 	{ 0x8086, 0x244e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_intel },
 	{ 0x8086, 0x245e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_intel },
 
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LX_AES,
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_geode },
+
 	{ 0, },	/* terminate list */
 };
 MODULE_DEVICE_TABLE (pci, rng_pci_tbl);
@@ -460,6 +477,53 @@ static void via_cleanup(void)
 }
 #endif
 
+/***********************************************************************
+ *
+ * AMD Geode RNG operations
+ *
+ */
+
+static void __iomem *geode_rng_base = NULL;
+
+#define GEODE_RNG_DATA_REG   0x50
+#define GEODE_RNG_STATUS_REG 0x54
+
+static u32 geode_data_read(void)
+{
+	u32 val;
+	assert(geode_rng_base != NULL);
+	val = readl(geode_rng_base + GEODE_RNG_DATA_REG);
+	return val;
+}
+
+static unsigned int geode_data_present(void)
+{
+	u32 val;
+	assert(geode_rng_base != NULL);
+	val = readl(geode_rng_base + GEODE_RNG_STATUS_REG);
+	return val;
+}
+
+static void geode_cleanup(void)
+{
+	iounmap(geode_rng_base);
+  	geode_rng_base = NULL;
+}
+
+static int geode_init(struct pci_dev *dev)
+{
+	unsigned long rng_base = pci_resource_start(dev, 0);
+	if (rng_base == NULL) return 1;
+
+	geode_rng_base = ioremap(rng_base, 0x58);
+
+	if (geode_rng_base == NULL) {
+		printk(KERN_ERR PFX "Cannot ioremap RNG memory\n");
+		return -EBUSY;
+	}
+
+	return 0;
+}
 
 /***********************************************************************
  *
@@ -574,7 +638,7 @@ static int __init rng_init (void)
 
 	DPRINTK ("ENTER\n");
 
-	/* Probe for Intel, AMD RNGs */
+	/* Probe for Intel, AMD, Geode RNGs */
 	for_each_pci_dev(pdev) {
 		ent = pci_match_id(rng_pci_tbl, pdev);
 		if (ent) {
#11 lore raw

PATCH 6/6 AMD Geode GX/LX Support (Refreshed)

In reply to a message not in the archive

The core IDE engine on the CS5536 is the same as the other AMD southbridges, so unlike the CS5535, we can simply add the appropriate PCI headers to the existing amd74xx code.

drivers/ide/pci/amd74xx.c |    3 +++
include/linux/pci_ids.h   |    9 +++++++++
2 files changed, 12 insertions(+)
drivers/ide/pci/amd74xx.c +3 -0
Index: linux-2.6.14/drivers/ide/pci/amd74xx.c
===================================================================
@@ -74,6 +74,7 @@ static struct amd_ide_chip {
 	{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE,	0x50, AMD_UDMA_133 },
 	{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE,	0x50, AMD_UDMA_133 },
 	{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE,	0x50, AMD_UDMA_133 },
+	{ PCI_DEVICE_ID_AMD_CS5536_IDE,             0x40, AMD_UDMA_100 },
 	{ 0 }
 };
 
@@ -491,6 +492,7 @@ static ide_pci_device_t amd74xx_chipsets
 	/* 14 */ DECLARE_NV_DEV("NFORCE-MCP04"),
 	/* 15 */ DECLARE_NV_DEV("NFORCE-MCP51"),
 	/* 16 */ DECLARE_NV_DEV("NFORCE-MCP55"),
+	/* 17 */ DECLARE_AMD_DEV("AMD5536"),
 };
 
 static int __devinit amd74xx_probe(struct pci_dev *dev, const struct pci_device_id *id)
@@ -527,6 +529,7 @@ static struct pci_device_id amd74xx_pci_
 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE,	PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14 },
 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE,	PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15 },
 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE,	PCI_ANY_ID, PCI_ANY_ID, 0, 0, 16 },
+	{ PCI_VENDOR_ID_AMD,    PCI_DEVICE_ID_AMD_CS5536_IDE, 	        PCI_ANY_ID, PCI_ANY_ID, 0, 0, 17 },
 	{ 0, },
 };
 MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl);
include/linux/pci_ids.h +9 -0
Index: linux-2.6.14/include/linux/pci_ids.h
===================================================================
@@ -546,6 +546,15 @@
 #define PCI_DEVICE_ID_AMD_LX_VIDEO  0x2081
 #define PCI_DEVICE_ID_AMD_LX_AES    0x2082
 
+#define PCI_DEVICE_ID_AMD_CS5536_ISA    0x2090
+#define PCI_DEVICE_ID_AMD_CS5536_FLASH  0x2091
+#define PCI_DEVICE_ID_AMD_CS5536_AUDIO  0x2093
+#define PCI_DEVICE_ID_AMD_CS5536_OHC    0x2094
+#define PCI_DEVICE_ID_AMD_CS5536_EHC    0x2095
+#define PCI_DEVICE_ID_AMD_CS5536_UDC    0x2096
+#define PCI_DEVICE_ID_AMD_CS5536_UOC    0x2097
+#define PCI_DEVICE_ID_AMD_CS5536_IDE    0x209A
+
 #define PCI_VENDOR_ID_TRIDENT		0x1023
 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX	0x2000
 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX	0x2001