amd76x_pm: C2 powersaving for AMD K7
Subsystems (2)
PATCH 1/2 amd76x_pm: C2 powersaving for AMD K7
This is a processor idle module for AMD SMP 760MP(X) based systems. The patch was originally written by Tony Lindgren and has been around since 2002. It enables C2 mode on AMD SMP systems and thus saves about 70 - 90 W of energy in the idle mode compared to the default idle mode. The idle function has been rewritten and is now free of locking issues and is independent from the number of CPUs. The impact from this module on the system clock and on i/o transfer rates has been reduced.
This patch can also be found at
http://www.sommrey.de/amd76x_pm/amd76x_pm-2.6.14-1.patch
Documentation/amd76x_pm.txt +341 -0
@@ -0,0 +1,341 @@ + ACPI style power management for SMP AMD-760MP(X) based systems + ============================================================== + +For use until the ACPI project catches up. :-) + +Using this module saves about 70 - 90W of energy in the idle mode compared +to the default idle mode. Waking up from the idle mode is fast to keep the +system response time good. Currently no CPU load calculation is done, the +system exits the idle mode after every C2 call. + +Known issues: +------------- +- Currently there's a bug somewhere where the reading the + P_LVL2 for the first time causes the system to sleep instead of + idling. This means that you need to hit the power button once to + wake the system after loading the module for the first time after + reboot. After that the system idles as supposed. + (Only observed on Tony's system.) + +- On kernel up to and including 2.6.13 there might appear a weird + keyboard repeating after an uptime of 1-2 days. This seems to + coincide with IRQ 0 being routed to CPU1: setting smp_affinity to 1 for + IRQ 0 soon after booting circumvents the problem. On 2.6.14 interrupt + routing has changed and I didn't watch the problem anymore. + +- There might be reduced throughput of disk or network devices. See + below for how to configure the "irq rate watcher" to avoid this. + +- I have a report of occasional hard lockups that might be caused by + amd76x_pm. + +Influenced by Vcool, and LVCool. Rewrote everything from scratch to +use the PCI features in Linux, and to support SMP systems. + +Currently tested amongst others on a TYAN S2460 (760MP) system (Tony), an +ASUS A7M266-D (760MPX) system (Johnathan) and a TYAN S2466 (760MPX) +system (Jo). Adding support for other Athlon SMP or single processor +systems should be easy if desired. + +The file /sys/devices/pci0000:00/0000:00:00.0/C2_cnt shows the number of +C2 calls since module load. + +There are some parameters for tuning the behaviour of amd76x_pm: +lazy_idle, spin_idle, watch_irqs, watch_int and min_C1 + +lazy_idle and spin_idle are closely related: + +- lazy_idle defines the number of idle calls into amd76x_smp_idle that are + needed to *enable* C2 mode. This parameter is the maximum loop counter + for an outer loop with interrupts enabled that guarantees low latencies. + The default for lazy_idle is 512. + +- spin_idle defines the maximum number of spin cycles in an inner idle loop + where one CPU waits for all others to get into C2-enabled mode. When all + CPUs are in C2-enable mode they (more ore less) simultaneously *enter* C2 + mode. In this inner loop interrupts are disabled. The loop is left + immediatly if there is something waiting to be scheduled. The default + for spin_idle is 2*lazy_idle. + +lazy_idle and spin_idle define a "rubber measure" for the idling +behaviour: lazy_idle defines the minimum "idling" needed to enter C2 and +spin_idle defines when to give up. + +Low values for lazy_idle and high values for spin_idle give better +cooling. Higher values for lazy_idle simply give less cooling. spin_idle +is a kind of emergency break to leave C2-enable mode if CPUs don't +synchronize. + +irq rate watcher: +----------------- +Interrupts are disabled in C2 mode. The CPUs are woken up by timer +interrups or by NMIs. This causes a high interrupt latency for other +interrupts that leads to a significant reduction in io or network +throughput. There has been introduced a "irq rate watcher" to reduce +this effect. If the irq rate watcher detects that an interrupt has a +rate above a given limit, C2 idling is disabled and a low latency C1 +idling mode is used instead. The parameters watch_irqs, watch_int and +min_C1 control this irq rate watcher: + +- watch_irqs defines which interrupts are to be watched and optionally + at which interrupt rate C2 mode shall be disabled. The syntax for + watch_irqs is irq1[:rate1],irq2[:rate2],... The rate is measured in + interrupts per second and defaults to 128. There is no default for + watch_irqs. To enable the irq rate watcher you must specify this + parameter. Enter the interrupts used by disk controllers or network + adapters here. + +- watch_int defines the time interval (in milliseconds) at which the + interrupt rate is checked. Too low values may result in an overhead + and too high values cause the C1 mode to "kick in" later. The default + for watch_int is 1 second. + +- min_C1 defines the mininum number of check intervals with low + interrupt rates that are needed to leave the forced C1 mode. + +All parameters lazy_idle, spin_idle, watch_irqs and watch_int may be +given as module parameters to amd76x_pm. Furthermore, they may be +queried or changed via their sysfs entries in +/sys/module/amd76x_pm/parameters. (The file location in sysfs has +changed from earlier versions!) + +Setting watch_int to zero or removing all interrupts from watch_irqs +causes the irq rate watcher to stop. The module needs to be reloaded to +start the watcher again. + +NB: In the past there was a major impact from amd76x_pm on the system +clock stability. At least on my box this effect has been reduced +noticable. This is caused by two changes: + +- The redesign of the idle function lead to a reduced time spent in + amd76x_smp_idle() and this propably caused lower latencies. + +- The introduction of the irq rate watcher significantly reduced + latencies under load. + +Some hints on tuning lazy_idle and spin_idle: +Watch the rate of C2 calls per second. Anything below HZ seems to be +completely useless. Start with a moderate low value for lazy_idle, e.g. +2^5 and a very high value for spin_idle, e.g. 2^20. Then double lazy_idle +until you see a significant increase in core temperature or C2 rate. +Go back to the last "good" value. Then halve spin_idle until you see +a decrease in C2 rate or a raising core temperature again and go back +to the previous value. There's a small program c2rate.c attached at the +end of this file that you may use to watch the C2 rate. The rtc driver +must be enabled to use it. + +There is an -extra patch available that adds some optional features: +- C3 idling: this works but is not well tested. +- normal throttling: untested for a long time. +- Power On Suspend: very experimental and untested. + +This software is licensed under GNU General Public License Version 2 +as specified in file COPYING in the Linux kernel source tree main +directory. + +Copyright (C) 2002 - 2005 Johnathan Hicks <[email protected]> + Tony Lindgren <[email protected]> + Joerg Sommrey <[email protected]> + +History: + + 20020702 - amd-smp-idle: Tony Lindgren <[email protected]> +Influenced by Vcool, and LVCool. Rewrote everything from scratch to +use the PCI features in Linux, and to support SMP systems. Provides +C2 idling on SMP AMD-760MP systems. + + 20020722: JH + I adapted Tony's code for the AMD-765/766 southbridge and adapted it + according to the AMD-768 data sheet to provide the same capability for + SMP AMD-760MPX systems. Posted to acpi-devel list. + + 20020722: Alan Cox + Replaces non-functional amd76x_pm code in -ac tree. + + 20020730: JH + Added ability to do normal throttling (the non-thermal kind), C3 idling + and Power On Suspend (S1 sleep). It would be very easy to tie swsusp + into activate_amd76x_SLP(). C3 idling doesn't happen yet; see my note + in amd76x_smp_idle(). I've noticed that when NTH and idling are both + enabled, my hardware locks and requires a hard reset, so I have + #ifndefed around the idle loop setting to prevent this. POS locks it up + too, both ought to be fixable. I've also noticed that idling and NTH + make some interference that is picked up by the onboard sound chip on + my ASUS A7M266-D motherboard. + + 20030601: Pasi Savolainen + Simple port to 2.5 + Added sysfs interface for making nice graphs with mrtg. + Look for /sys/devices/pci0/00:00.0/C2_cnt & lazy_idle (latter writable) + + 20050601: Joerg Sommrey (jo) + 2.6 stuff + redesigned amd76x_smp_idle. The algorithm is basically the same + but the implementation has changed. This part is now independent + from the number of CPUs and data is locked against concurrent + updates from different CPUs. + use _smp_processor_id() + use cpu_idle_wait() + NTH and POS code not touched and not tested. + + 20050621: jo + separated C3, NTH and POS code into extra patch + + 20050812: jo + rewritten amd76x_smp_idle completely. It's much simpler now but + does a good job - the KISS approach. Introduced a new tunable + spin_idle. + + 20050819: jo + new irq rate watcher task that forces C1-idling if irq-rate exceeds a + given limit. + + 20050820: jo + make all modules parameters r/w in sysfs. + + 20050906: jo + avoid some local_irq_disable/enable + +TODO: Thermal throttling (TTH). + /proc interface for normal throttling level. + /proc interface for POS. + +---- c2rate.c ---- snip here ---------------------------------------- +/* c2rate.c + * usage: c2rate [interval] + * interval is the time in seconds between two calculations and defaults + * to 16 + * You may #define C3 if you're playing with C3 mode. + */ +#include <stdlib.h> +#include <stdio.h> +#include <linux/rtc.h> +#include <sys/ioctl.h> +#include <sys/time.h> +#include <sys/types.h> +#include <fcntl.h> +#include <unistd.h> +#include <errno.h> + +#define C2_CNT "/sys/devices/pci0000:00/0000:00:00.0/C2_cnt" +#define C3_CNT "/sys/devices/pci0000:00/0000:00:00.0/C3_cnt" +// #define C3 +int fd; + +void +disable_rtc(void) { + int retval; + /* Disable alarm interrupts */ + retval = ioctl(fd, RTC_UIE_OFF, 0); + if (retval == -1) { + perror("ioctl(RTC_UIE_OFF)"); + _exit(errno); + } + close(fd); +} + +int +main(int argc, char **argv) +{ + int retval; + unsigned long data; + char idlebuffer[64]; + int idlefd; + ssize_t bytes; + unsigned long lastcount; + unsigned long irqcount; + unsigned long c2_old, c2_new; +#ifdef C3 + unsigned long c3_old, c3_new; +#endif + int rate = 0; + int firstloop = 1; + + if(argc > 1) + rate = atoi(argv[1]); + if (rate <= 0) + rate = 16; + + fd = open ("/dev/rtc", O_RDONLY); + + if (fd == -1) { + perror("/dev/rtc"); + exit(errno); + } + + /* Set the alarm to every second */ + + retval = ioctl(fd, RTC_UIE_ON, 0); + if (retval == -1) { + perror("ioctl(RTC_UIE_ON)"); + exit(errno); + } + atexit(disable_rtc); + + irqcount = 0; + while (1) { + /* This blocks until the alarm ring causes an interrupt */ + retval = read(fd, &data, sizeof data); + if (retval == -1) { + perror("read"); + exit(errno); + } + if (firstloop) { + idlebuffer[0] = '\0'; + idlefd = open(C2_CNT, O_RDONLY); + if (idlefd != -1) { + bytes = read(idlefd, idlebuffer, sizeof idlebuffer); + close(idlefd); + idlebuffer[bytes] = '\0'; + } + c2_old = strtoul(idlebuffer, NULL, 10); +#ifdef C3 + idlebuffer[0] = '\0'; + idlefd = open(C3_CNT, O_RDONLY); + if (idlefd != -1) { + bytes = read(idlefd, idlebuffer, sizeof idlebuffer); + close(idlefd); + idlebuffer[bytes] = '\0'; + } + c3_old = strtoul(idlebuffer, NULL, 10); +#endif + firstloop = 0; + continue; + } + lastcount = data >> 8; + irqcount += lastcount; + + if (irqcount >= rate) { + idlebuffer[0] = '\0'; + idlefd = open(C2_CNT, O_RDONLY); + if (idlefd != -1) { + bytes = read(idlefd, idlebuffer, sizeof idlebuffer); + close(idlefd); + idlebuffer[bytes] = '\0'; + } + c2_new = strtoul(idlebuffer, NULL, 10); +#ifdef C3 + idlebuffer[0] = '\0'; + idlefd = open(C3_CNT, O_RDONLY); + if (idlefd != -1) { + bytes = read(idlefd, idlebuffer, sizeof idlebuffer); + close(idlefd); + idlebuffer[bytes] = '\0'; + } + c3_new = strtoul(idlebuffer, NULL, 10); + printf("%lu\t%lu\n", (c2_new - c2_old) / irqcount, + (c3_new - c3_old) / irqcount); + c3_old = c3_new; +#else + printf("%lu\n", (c2_new - c2_old) / irqcount); +#endif + c2_old = c2_new; + irqcount = 0; + } + + } + + return 0; + +} /* end main */ +---- c2rate.c ---- snip here ----------------------------------------
drivers/acpi/Kconfig +14 -0
@@ -341,4 +341,18 @@ $>modprobe acpi_memhotplug endif # ACPI +config AMD76X_PM + tristate "AMD76x Native Power Management support" + default n + depends on X86 && PCI + ---help--- + This driver enables Power Management on AMD760MP & AMD760MPX chipsets. This is about same as ACPI C2, except that ACPI folks don't do SMP ATM. + See Documentation/amd76x_pm.txt for further details. + + To compile this driver as a module ( = code which can be inserted in + and removed from the running kernel whenever you want), say M + here. The module will be called amd76x_pm. + + If unsure, say N. + endmenu
drivers/acpi/Kconfig.orig +344 -0
344 lines not on this page · raw message
drivers/acpi/Makefile +5 -0
@@ -57,3 +57,8 @@ obj-$(CONFIG_ACPI_TOSHIBA) += toshiba_acpi.o obj-y += scan.o motherboard.o obj-$(CONFIG_ACPI_HOTPLUG_MEMORY) += acpi_memhotplug.o + +# +# not really ACPI thing, until they handle SMP. +# +obj-$(CONFIG_AMD76X_PM) += amd76x_pm.o
drivers/acpi/Makefile.orig +59 -0
59 lines not on this page · raw message
drivers/acpi/amd76x_pm.c +647 -0
647 lines not on this page · raw message
include/linux/amd76x_pm.h +63 -0
63 lines not on this page · raw message
PATCH 2/2 amd76x_pm: C2 powersaving for AMD K7
This patch adds some experimental features to amd76x_pm, namely C3, NTH and POS support. These features are not enabled by default and are intended for kernel hackers only.
This patch can also be found at
http://www.sommrey.de/amd76x_pm/amd76x_pm-2.6.14-1-extra.patch
drivers/acpi/amd76x_pm.c renamed from drivers/acpi/amd76x_pm.c.orig +301 -1
@@ -59,12 +59,17 @@#include <linux/amd76x_pm.h> -#define VERSION "20050906" +#define VERSION "20050906-extra" +// #define AMD76X_NTH 1 +// #define AMD76X_POS 1 +// #define AMD76X_C3 1 // #define AMD76X_LOG_C1 1 extern void default_idle (void ); +#ifndef AMD76X_NTH static void amd76x_smp_idle (void ); +#endif static int amd76x_pm_main (void );static unsigned long lazy_idle =0 ;
@@ -72,8 +77,10 @@static unsigned long watch_int =0 ;static unsigned long min_C1 =AMD76X_MIN_C1 ; +#ifndef AMD76X_NTH static int show_watch_irqs (char *,struct kernel_param *);static int set_watch_irqs (const char *,struct kernel_param *); +#endif module_param (lazy_idle, long,S_IRUGO |S_IWUSR );
@@ -84,6 +91,7 @@MODULE_PARM_DESC (spin_idle,"\tnumber of spin cycles to wait for other CPUs to become idle" ); +#ifndef AMD76X_NTH module_param (watch_int, long,S_IRUGO |S_IWUSR );MODULE_PARM_DESC (watch_int,"\twatch interval (in milliseconds) for interrupts" );
@@ -94,6 +102,7 @@"\tlist of irqs (and optional their limit per second) that " "cause fallback to C1 mode. " "Syntax: irq0[:limit0],irq1[:limit1],..."); +#endif module_param (min_C1, long,S_IRUGO |S_IWUSR ); MODULE_PARM_DESC(min_C1,
@@ -110,6 +119,12 @@struct PM_cfg {unsigned int status_reg;unsigned int C2_reg; +#ifdef AMD76X_C3 +unsigned int C3_reg; +#endif +#ifdef AMD76X_NTH +unsigned int NTH_reg; +#endif unsigned int slp_reg;unsigned int resume_reg;void (*orig_idle) (void );
@@ -118,21 +133,34 @@ static struct PM_cfg amd76x_pm_cfg __cacheline_aligned_in_smp; +#ifndef AMD76X_NTH struct idle_stat {atomic_t num_idle; +#ifdef AMD76X_C3 +atomic_t num_C2; +#endif }; static struct idle_stat amd76x_stat __cacheline_aligned_in_smp = { .num_idle =ATOMIC_INIT (0 ), +#ifdef AMD76X_C3 + .num_C2 =ATOMIC_INIT (0 ) +#endif };struct cpu_stat {int idle_count;int C2_cnt; +#ifdef AMD76X_C3 +int C3_cnt; +int C2_active; +#else int _fill[2 ]; +#endif }; static struct cpu_stat prs[NR_CPUS] __cacheline_aligned_in_smp; +#endif struct watch_item {int irq;
@@ -216,7 +244,13 @@ regdword &=0xff80 ; amd76x_pm_cfg.status_reg = (regdword +0x00 ); amd76x_pm_cfg.slp_reg = (regdword +0x04 ); +#ifdef AMD76X_NTH + amd76x_pm_cfg.NTH_reg = (regdword +0x10 ); +#endif amd76x_pm_cfg.C2_reg = (regdword +0x14 ); +#ifdef AMD76X_C3 + amd76x_pm_cfg.C3_reg = (regdword +0x15 ); +#endif amd76x_pm_cfg.resume_reg = (regdword +0x16 );/* N/A for 768 */ }
@@ -261,6 +295,52 @@ regdword &= ~((STPCLK_EN |CPUSLP_EN ) <<C2_REGS );pci_write_config_dword (pdev_sb,0x50 , regdword); } +#ifdef AMD76X_C3 +/* +* Untested C3 idle support for AMD-766. +*/ +static void +config_amd766_C3 (int enable) +{ +unsigned int regdword; + +/* Set C3 options in C3A50, page 63 in AMD-766 doc */ +pci_read_config_dword (pdev_sb,0x50 , ®dword); +if (enable) { + regdword &= ~((DCSTOP_EN |PCISTP_EN |SUSPND_EN |CPURST_EN ) + <<C3_REGS ); + regdword |= (STPCLK_EN /* ~ 20 Watt savings max */ + |CPUSLP_EN /* Additional ~ 70 Watts max! */ + |CPUSTP_EN )/* yet more savings! */ + <<C3_REGS ; + } +else + regdword &= ~((STPCLK_EN |CPUSLP_EN |CPUSTP_EN ) <<C3_REGS ); +pci_write_config_dword (pdev_sb,0x50 , regdword); +} +#endif + + +#ifdef AMD76X_POS +static void +config_amd766_POS (int enable) +{ +unsigned int regdword; + +/* Set C3 options in C3A50, page 63 in AMD-766 doc */ +pci_read_config_dword (pdev_sb,0x50 , ®dword); +if (enable) { + regdword &= ~((ZZ_CACHE_EN |CPURST_EN ) <<POS_REGS ); + regdword |= ((DCSTOP_EN |STPCLK_EN |CPUSTP_EN |PCISTP_EN | +CPUSLP_EN |SUSPND_EN ) <<POS_REGS ); + } +else + regdword ^= (0xff <<POS_REGS ); +pci_write_config_dword (pdev_sb,0x50 , regdword); +} +#endif + +/* * Configures the 765 & 766 southbridges.
@@ -271,6 +351,13 @@amd76x_get_PM ();config_PMIO_amd76x (1 ,1 );config_amd766_C2 (enable); +#ifdef AMD76X_C3 +config_amd766_C3 (enable); +#endif + +#ifdef AMD76X_POS +config_amd766_POS (enable); +#endif return 0 ; }
@@ -293,6 +380,69 @@pci_write_config_byte (pdev_sb,0x4F , regbyte); } +#ifdef AMD76X_C3 +/* +* C3 idle support for AMD-768. The idle loop would need some extra +* handling for C3, but it would make more sense for ACPI to handle CX level +* transitions like it is supposed to. Unfortunately ACPI doesn't do CX +* levels on SMP systems yet. +*/ +static void +config_amd768_C3 (int enable) +{ +unsigned char regbyte; + +/* Set C3 options in DevB:3x4F, page 100 in AMD-768 doc */ +pci_read_config_byte (pdev_sb,0x4F , ®byte); +if (enable) + regbyte |= (C3EN /* | ZZ_C3EN | CSLP_C3EN | CSTP_C3EN */ ); +else + regbyte ^=C3EN ; +pci_write_config_byte (pdev_sb,0x4F , regbyte); +} +#endif + +#ifdef AMD76X_POS +/* +* Untested Power On Suspend support for AMD-768. This should also be handled +* by ACPI. +*/ +static void +config_amd768_POS (int enable) +{ +unsigned int regdword; + +/* Set POS options in DevB:3x50, page 101 in AMD-768 doc */ +pci_read_config_dword (pdev_sb,0x50 , ®dword); +if (enable) + regdword |= (POSEN |CSTP |PSTP |ASTP |DCSTP |CSLP |SUSP ); +else + regdword ^=POSEN ; +pci_write_config_dword (pdev_sb,0x50 , regdword); +} +#endif + + +#ifdef AMD76X_NTH +/* +* Normal Throttling support for AMD-768. There are several settings +* that can be set depending on how long you want some of the delays to be. +* I'm not sure if this is even neccessary at all as the 766 doesn't need this. +*/ +static void +config_amd768_NTH (int enable,int ntper,int thminen) +{ +unsigned char regbyte; + +/* DevB:3x40, pg 93 of 768 doc */ +pci_read_config_byte (pdev_sb,0x40 , ®byte); +/* Is it neccessary to use THMINEN at ANY time? */ + regbyte |= (NTPER (ntper) |THMINEN (thminen)); +pci_write_config_byte (pdev_sb,0x40 , regbyte); +} +#endif + +/* * Configures the 768 southbridge to support idle calls, and gets * the processor idle call register location.
@@ -305,10 +455,64 @@config_PMIO_amd76x (0 ,1 );config_amd768_C2 (enable); +#ifdef AMD76X_C3 +config_amd768_C3 (enable); +#endif +#ifdef AMD76X_POS +config_amd768_POS (enable); +#endif +#ifdef AMD76X_NTH +config_amd768_NTH (enable,1 ,2 ); +#endif return 0 ; } +#ifdef AMD76X_NTH +/* +* Activate normal throttling via its ACPI register (P_CNT). +*/ +static void +activate_amd76x_NTH (int enable,int ratio) +{ +unsigned int regdword; + +/* PM10, pg 110 of 768 doc, pg 70 of 766 doc */ + regdword=inl (amd76x_pm_cfg.NTH_reg); +if (enable) + regdword |= (NTH_EN |NTH_RATIO (ratio)); +else + regdword ^=NTH_EN ; +outl (regdword, amd76x_pm_cfg.NTH_reg); +} +#endif + +#ifdef AMD76X_POS +/* +* Activate sleep state via its ACPI register (PM1_CNT). +*/ +static void +activate_amd76x_SLP (int type) +{ +unsigned short regshort; + +/* PM04, pg 109 of 768 doc, pg 69 of 766 doc */ + regshort=inw (amd76x_pm_cfg.slp_reg); + regshort |= (SLP_EN |SLP_TYP (type)) ; +outw (regshort, amd76x_pm_cfg.slp_reg); +} +#endif /* AMD76X_POS */ +#ifdef AMD76X_POS +/* +* Wrapper function to activate POS sleep state. +*/ +static void +activate_amd76x_POS (void ) +{ +activate_amd76x_SLP (1 ); +} +#endif +/* * Idle loop for single processor systems */
@@ -321,6 +525,7 @@ amd76x_pm_cfg.orig_idle (); } +#ifndef AMD76X_NTH /* * Idle loop for SMP systems *
@@ -367,9 +572,30 @@smp_mb ();if (unlikely (atomic_read (&amd76x_stat.num_idle) == num_online)) { +#ifdef AMD76X_C3 +/* Enter C3 if all CPUs are ready for C3. +* Enter C2 otherwise. +*/ +if (unlikely (atomic_read (&amd76x_stat.num_C2) == + num_online)) { +/* Invoke C3 */ + prs[cpu].C3_cnt++; +inb (amd76x_pm_cfg.C3_reg); + }else { +/* Invoke C2 */ + prs[cpu].C2_cnt++; +inb (amd76x_pm_cfg.C2_reg); +/* Now we are ready for C3 */ +if (!prs[cpu].C2_active) { + prs[cpu].C2_active =1 ; +atomic_inc (&amd76x_stat.num_C2); + } + } +#else /* Invoke C2 */ prs[cpu].C2_cnt++;inb (amd76x_pm_cfg.C2_reg); +#endif smp_mb ();atomic_dec (&amd76x_stat.num_idle); prs[cpu].idle_count =0 ;
@@ -380,13 +606,24 @@smp_mb ();atomic_dec (&amd76x_stat.num_idle); +#ifdef AMD76X_C3 +/* We haven't been in C2/C3 if we are here. We are no longer +* ready for C3. +*/ +if (prs[cpu].C2_active) { + prs[cpu].C2_active =0 ; +atomic_dec (&amd76x_stat.num_C2); + } +#endif prs[cpu].idle_count =0 ;local_irq_enable (); } +#endif /* * sysfs support, RW */ +#ifndef AMD76X_NTH static int show_watch_irqs (char *buf,struct kernel_param *kp) {
@@ -460,8 +697,26 @@return sprintf (buf,"%u\n" , C2_cnt); } +#ifdef AMD76X_C3 +static ssize_t +show_C3_cnt (struct device *dev,struct device_attribute *attr, +char *buf) +{ +unsigned int C3_cnt =0 ; +int i; +for_each_online_cpu (i) + C3_cnt += prs[i].C3_cnt; +return sprintf (buf,"%u\n" , C3_cnt); +} +#endif + static DEVICE_ATTR(C2_cnt, S_IRUGO, show_C2_cnt, NULL); +#ifdef AMD76X_C3 +static DEVICE_ATTR(C3_cnt, S_IRUGO, + show_C3_cnt, NULL); +#endif +#endif static void setup_watch (void )
@@ -519,7 +774,9 @@static int amd76x_pm_main (void ) { +#ifndef AMD76X_NTH int i; +#endif amd76x_pm_cfg.orig_idle =0 ;if (lazy_idle ==0 )
@@ -572,13 +829,16 @@switch (pdev_nb->device) {case PCI_DEVICE_ID_AMD_FE_GATE_700C :/* AMD-762 */ config_amd762 (1 ); +#ifndef AMD76X_NTH amd76x_pm_cfg.curr_idle = amd76x_smp_idle; +#endif break ;default :printk (KERN_ERR "amd76x_pm: No northbridge to initialize\n" );break ; } +#ifndef AMD76X_NTH if (num_online_cpus () ==1 ) { amd76x_pm_cfg.curr_idle = amd76x_up_idle;printk (KERN_ERR "amd76x_pm: UP machine detected. ACPI is your friend.\n" );
@@ -591,6 +851,10 @@for (i =0 ; i <NR_CPUS ; i++) { prs[i].idle_count =0 ; prs[i].C2_cnt =0 ; +#ifdef AMD76X_C3 + prs[i].C3_cnt =0 ; + prs[i].C2_active =0 ; +#endif } amd76x_pm_cfg.orig_idle = pm_idle;
@@ -600,7 +864,20 @@/* sysfs */ device_create_file (&pdev_nb->dev, &dev_attr_C2_cnt); +#ifdef AMD76X_C3 +device_create_file (&pdev_nb->dev, &dev_attr_C3_cnt); +#endif +#endif +#ifdef AMD76X_NTH +/* Turn NTH on with maxium throttling for testing. */ +activate_amd76x_NTH (1 ,1 ); +#endif + +#ifdef AMD76X_POS +/* Testing here only. */ +activate_amd76x_POS (); +#endif setup_watch ();return 0 ;
@@ -618,9 +895,15 @@ static void __exitamd76x_pm_cleanup (void ) { +#ifndef AMD76X_NTH int i;unsigned int C2_cnt =0 ; +#ifdef AMD76X_C3 +unsigned int C3_cnt =0 ; +#endif +#endif +#ifndef AMD76X_NTH pm_idle = amd76x_pm_cfg.orig_idle;cpu_idle_wait ();
@@ -629,11 +912,28 @@/* This isn't really needed. */ for_each_online_cpu (i) { C2_cnt += prs[i].C2_cnt; +#ifdef AMD76X_C3 + C3_cnt += prs[i].C3_cnt; +#endif } +#ifdef AMD76X_C3 +printk (KERN_INFO "amd76x_pm: %u C2 calls, %u C3 calls\n" , + C2_cnt, C3_cnt); +#else printk (KERN_INFO "amd76x_pm: %u C2 calls\n" , C2_cnt); +#endif /* remove sysfs */ device_remove_file (&pdev_nb->dev, &dev_attr_C2_cnt); +#ifdef AMD76X_C3 +device_remove_file (&pdev_nb->dev, &dev_attr_C3_cnt); +#endif +#endif + +#ifdef AMD76X_NTH +/* Turn NTH off*/ +activate_amd76x_NTH (0 ,0 ); +#endif irqwatch.schedule =0 ;flush_scheduled_work ();