Correct register for pci async mode on PPC440EP

PATCH New Youngchul Bang 2 participants 2 messages Dec 8, 2005 – Dec 10, 2005

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Youngchul Bang

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2005-12-08 08:35 UTC #0 lore raw

PATCH 1/1 Correct register for pci async mode on PPC440EP

Hi, Stefan

This patch fixes the register for PCI async mode configuration information.

Best regards,
Youngchul Bang

cpu/ppc4xx/cpu.c +1 -1

index a463053..a26533c 100644
@@ -57,7 +57,7 @@ int pci_async_enabled(void)
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
        unsigned long val;
 
-       mfsdr(cpc0_strp1, val);
+       mfsdr(sdr_sdstp1, val);
        return (val & SDR0_SDSTP1_PAME_MASK);
 #endif
 }

Stefan Roese

2005-12-10 08:02 UTC #1 lore raw

PATCH 1/1 Correct register for pci async mode on PPC440EP

Hi Youngchul,

Quoted 1 line · Youngchul Bang

This patch fixes the register for PCI async mode configuration information.

Thanks! I seem to have missed this. Will be checked in soon.

Best regards,
Stefan