fix interrupt handling for R2 CPUs
PATCH 1/1 fix interrupt handling for R2 CPUs
This patch ensures that
a) only the low bit is used for status flags if CONFIG_CPU_MIPSR2, consistent with the use of di/ei.
b) the ERL/EXL bits get cleared as well.
Signed-off-by Thiemo Seufer <[email protected]>
include/asm-mips/interrupt.h +4 -1
@@ -102,6 +102,9 @@ __asm__ (" mfc0 \\flags, $2, 1 \n" #else" mfc0 \\flags, $12 \n" +#ifdef CONFIG_CPU_MIPSR2 + " andi \\flags, 1 \n" +#endif #endif " .set pop \n" " .endm \n");
@@ -169,7 +172,7 @@ __asm__ (* Fast, dangerous. Life is fun, life is good. */ " mfc0 $1, $12 \n" -" ins $1, \\flags, 0, 1 \n" +" ins $1, \\flags, 0, 5 \n" " mtc0 $1, $12 \n"#else " mfc0 $1, $12 \n"
Quoted 4 lines · Thiemo Seufer
a) only the low bit is used for status flags if
CONFIG_CPU_MIPSR2, consistent with the use of di/ei.b) the ERL/EXL bits get cleared as well.
Does this patch make a difference for you anywhere?
Ralf
Quoted 8 lines · Ralf Baechle
Quoted 4 lines · Thiemo Seufer
a) only the low bit is used for status flags if
CONFIG_CPU_MIPSR2, consistent with the use of di/ei.b) the ERL/EXL bits get cleared as well.
Does this patch make a difference for you anywhere?
It fixes a MIPS32R2-compiled qemu kernel for me which broke when the new bitfield instructions were added.
Thiemo