sparc32: max_cache_size fallback

From: Krzysztof Helt ([email protected])

It adds a fallback for CPU cache size detection. According to Sun documentation, it is possible to have SMP system with SM40 modules.

---

It is added after sparc64 architecture.

Regards,
Krzysztof

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diff -urp linux-2.6.17/arch/sparc/kernel/smp.c linux-new/arch/sparc/kernel/smp.c
@@ -79,6 +78,9 @@ void __cpuinit smp_store_cpu_info(int id
 		cache_nlines = 0x8000;
 		cache_nlines = prom_getintdefault(cpu_node, "ecache-nlines", cache_nlines);
 		max_cache_size = cache_line * cache_nlines;
+		/* this is for SM40 SuperSparc modules */
+		if (max_cache_size == 0)
+			max_cache_size = 36 * 1024;
 	}
 	if (cpu_data(id).mid < 0)
 		panic("No MID found for CPU%d at node 0x%08d", id, cpu_node);

From: "Krzysztof Helt" <[email protected]>
Date: Sat, 12 Aug 2006 21:14:44 +0200

This new fallback is "36 * 1024", ie. 36K? That doesn't make any sense. I thought the smallest SM40 cache size was 512K or something like that.

If anything it should be a power of two, not some weird number like 36K.

Dnia 26-08-2006 o godz. 1:24 David Miller napisa³(a):

something

According to the documentation I found ("Supersparc II Addendum" by Sun), the Supersparc processors have 20KB instruction cache and 16 KB data cache on CPU. The SMX0 modules were modules without the L2 cache so only cache on CPU is counted.

That max_cache_size counting procedure counts only L2 cache as it is much bigger than L1. Thus for SMX0 modules it may give 0 (I have no such SMP machine to test). At least one SMP configuration was sold with such CPUs - it was called SparcStation 10/402 (it can be found mentioned on specrate listings).

I peeked into the i386 code and found that for original Pentium the max_cache_size is set to 16KB. The Pentium has 8KB instruction cache and 8KB data cache (both L1 as it has no L2 on he CPU). So I did the same for the Supersparcs.

I added 20KB and 16Kb and got 36KB total cache size.

Regards,
Krzysztof

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From: "Krzysztof Helt" <[email protected]>
Date: Sat, 26 Aug 2006 10:59:23 +0200

I think you should just use the data cache size on these L2'less chips.

From: Krzysztof Helt ([email protected])

It adds a fallback for CPU cache size detection. According to Sun documentation, it is possible to have SMP system with SM40 modules. It counts only data cache after David Miller suggestion.

---

I don't think that counting only data cache is right but it does not matter as scheduler do not use values lesser than 64KB (it uses 64KB instead).

Regards,
Krzysztof

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diff -urp linux-2.6.17/arch/sparc/kernel/smp.c linux-new/arch/sparc/kernel/smp.c
@@ -79,6 +78,9 @@ void __cpuinit smp_store_cpu_info(int id
 		cache_nlines = 0x8000;
 		cache_nlines = prom_getintdefault(cpu_node, "ecache-nlines", cache_nlines);
 		max_cache_size = cache_line * cache_nlines;
+		/* this is for SM40 SuperSparc modules */
+		if (max_cache_size == 0)
+			max_cache_size = 16 * 1024;
 	}
 	if (cpu_data(id).mid < 0)
 		panic("No MID found for CPU%d at node 0x%08d", id, cpu_node);