Making PCI Memory Cachable

I have numerous custom PCI devices that implement SRAM or DRAM on the PCI bus. I would like to explore making this memory cachable in the hopes that writes to memory can be done from user space and will be done in bursts rather than single cycles.

Is this crazy or what? I assumed that the VM_IO flag in remap_pfn_range controls this, but that doesn't appear to be the case.

A simple test from user space is the following:
ptr = mmap(...)
memset(ptr, 'a', size)

The driver gets the pointer with remap_pfn_range, but I always see 64-bit writes to memory (this is x86_64 architecture). If this were cachable and the HW waqs cooperative, I would expect to see cache line bursts (e.g. 128 bytes).

I think one of two things is happening:
a) The kernel is not making this memory cachable
b) The memory is cachable, but the chipset is throttling the bursts

Can someone enlighten me?

Thanks,
John

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You want write combining, not cacheable. The only way to do this currently is to set a MTRR. See Documentation/mtrr.txt by default.

The normal cache coherency protocol doesn't work over PCI

-Andi

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