clock_event patches for arm systems

Index: arch/arm/mach-imx/time.c
===================================================================
@@ -15,6 +15,7 @@
 #include <linux/irq.h>
 #include <linux/time.h>
 #include <linux/clocksource.h>
+#include <linux/clockchips.h>
 
 #include <asm/hardware.h>
 #include <asm/io.h>

@@ -25,7 +26,52 @@
 /* Use timer 1 as system timer */
 #define TIMER_BASE IMX_TIM1_BASE
 
-static unsigned long evt_diff;
+enum clock_event_mode clockevent_mode = 0;
+
+static void imx_set_next_event(unsigned long evt,
+			       struct clock_event_device *unused)
+{
+	IMX_TCMP(IMX_TIM1_BASE) = IMX_TCN(IMX_TIM1_BASE) + evt;
+}
+
+static void imx_set_mode(enum clock_event_mode mode,
+			 struct clock_event_device *evt)
+{
+	switch (mode) {
+	case CLOCK_EVT_PERIODIC:
+	case CLOCK_EVT_ONESHOT:
+		IMX_TCTL(TIMER_BASE) |= TCTL_IRQEN;
+		break;
+
+	case CLOCK_EVT_SHUTDOWN:
+		IMX_TCTL(TIMER_BASE) &= ~TCTL_IRQEN;
+		return;
+	}
+
+	clockevent_mode = mode;
+}
+
+static struct clock_event_device clockevent_imx = {
+	.name		= "imx_timer1",
+	.capabilities	= CLOCK_CAP_NEXTEVT | CLOCK_CAP_TICK |
+			  CLOCK_CAP_UPDATE | CLOCK_CAP_PROFILE,
+	.shift		= 32,
+	.set_mode	= imx_set_mode,
+	.set_next_event	= imx_set_next_event,
+};
+
+static int __init imx_clockevent_init(void)
+{
+	clockevent_imx.mult = div_sc(imx_get_perclk1(), NSEC_PER_SEC,
+					clockevent_imx.shift);
+	clockevent_imx.max_delta_ns =
+		clockevent_delta2ns(0xfffffffe, &clockevent_imx);
+	clockevent_imx.min_delta_ns =
+		clockevent_delta2ns(0xf, &clockevent_imx);
+	register_local_clockevent(&clockevent_imx);
+
+	return 0;
+}
 
 /*
  * IRQ handler for the timer

@@ -42,10 +88,12 @@ imx_timer_interrupt(int irq, void *dev_i
 	if (tstat & TSTAT_COMP) {
 		do {
 
-			write_seqlock(&xtime_lock);
-			timer_tick();
-			write_sequnlock(&xtime_lock);
-			IMX_TCMP(TIMER_BASE) += evt_diff;
+			clockevent_imx.event_handler();
+
+			if (clockevent_mode != CLOCK_EVT_PERIODIC)
+				break;
+
+			IMX_TCMP(TIMER_BASE) += LATCH;
 
 		} while (unlikely((int32_t)(IMX_TCMP(TIMER_BASE)
 					- IMX_TCN(TIMER_BASE)) < 0));

@@ -70,10 +118,8 @@ static void __init imx_timer_hardware_in
 	 */
 	IMX_TCTL(TIMER_BASE) = 0;
 	IMX_TPRER(TIMER_BASE) = 0;
-	IMX_TCMP(TIMER_BASE) = LATCH - 1;
-
-	IMX_TCTL(TIMER_BASE) = TCTL_FRR | TCTL_CLK_PCLK1 | TCTL_IRQEN | TCTL_TEN;
-	evt_diff = LATCH;
+	IMX_TCMP(TIMER_BASE) = LATCH;
+	IMX_TCTL(TIMER_BASE) = TCTL_FRR | TCTL_CLK_PCLK1 | TCTL_TEN | TCTL_IRQEN;
 }
 
 cycle_t imx_get_cycles(void)

@@ -82,12 +128,12 @@ cycle_t imx_get_cycles(void)
 }
 
 static struct clocksource clocksource_imx = {
-	.name 		= "imx_timer1",
+	.name		= "imx_timer1",
 	.rating		= 200,
 	.read		= imx_get_cycles,
 	.mask		= 0xFFFFFFFF,
-	.shift 		= 20,
-	.is_continuous 	= 1,
+	.shift		= 20,
+	.is_continuous	= 1,
 };
 
 static int __init imx_clocksource_init(void)

@@ -103,6 +149,7 @@ static void __init imx_timer_init(void)
 {
 	imx_timer_hardware_init();
 	imx_clocksource_init();
+	imx_clockevent_init();
 
 	/*
 	 * Make irqs happen for the system timer

Index: arch/arm/mach-netx/time.c
===================================================================
@@ -21,27 +21,65 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/clocksource.h>
+#include <linux/clockchips.h>
 
 #include <asm/hardware.h>
 #include <asm/io.h>
 #include <asm/mach/time.h>
 #include <asm/arch/netx-regs.h>
 
+static void netx_set_next_event(unsigned long evt,
+				  struct clock_event_device *unused)
+{
+	writel(0 - evt, NETX_GPIO_COUNTER_CURRENT(0));
+}
+
+static void netx_set_mode(enum clock_event_mode mode,
+			  struct clock_event_device *evt)
+{
+	u32 tmode = NETX_GPIO_COUNTER_CTRL_IRQ_EN | NETX_GPIO_COUNTER_CTRL_RUN;
+
+	/* disable timer */
+	writel( 0, NETX_GPIO_COUNTER_CTRL(0));
+
+	switch(mode) {
+	case CLOCK_EVT_PERIODIC:
+		/* Set timer period  */
+		writel(LATCH, NETX_GPIO_COUNTER_MAX(0));
+		tmode |= NETX_GPIO_COUNTER_CTRL_RST_EN;
+		break;
+
+	case CLOCK_EVT_ONESHOT:
+		writel(0, NETX_GPIO_COUNTER_MAX(0));
+		break;
+
+	case CLOCK_EVT_SHUTDOWN:
+		return;
+	}
+
+	writel(tmode, NETX_GPIO_COUNTER_CTRL(0));
+}
+
+static struct clock_event_device clockevent_netx = {
+	.name		= "netx_timer1",
+	.capabilities	= CLOCK_CAP_NEXTEVT | CLOCK_CAP_TICK |
+			  CLOCK_CAP_UPDATE | CLOCK_CAP_PROFILE,
+	.shift		= 32,
+	.set_mode	= netx_set_mode,
+	.set_next_event	= netx_set_next_event,
+};
+
 /*
  * IRQ handler for the timer
  */
 static irqreturn_t
 netx_timer_interrupt(int irq, void *dev_id)
 {
-	write_seqlock(&xtime_lock);
-
-	timer_tick();
-
-	write_sequnlock(&xtime_lock);
-
 	/* acknowledge interrupt */
 	writel(COUNTER_BIT(0), NETX_GPIO_IRQ);
 
+	clockevent_netx.event_handler();
+
 	return IRQ_HANDLED;
 }
 

@@ -57,12 +95,12 @@ cycle_t netx_get_cycles(void)
 }
 
 static struct clocksource clocksource_netx = {
-	.name 		= "netx_timer",
+	.name		= "netx_timer",
 	.rating		= 200,
 	.read		= netx_get_cycles,
 	.mask		= CLOCKSOURCE_MASK(32),
-	.shift 		= 20,
-	.is_continuous 	= 1,
+	.shift		= 20,
+	.is_continuous	= 1,
 };
 
 /*

@@ -81,24 +119,34 @@ static void __init netx_timer_init(void)
 	/* acknowledge interrupt */
 	writel(COUNTER_BIT(0), NETX_GPIO_IRQ);
 
-	/* Enable the interrupt in the specific timer register and start timer */
+	/* Enable the interrupt in the specific timer register and
+	 * start timer
+	 */
 	writel(COUNTER_BIT(0), NETX_GPIO_IRQ_ENABLE);
 	writel(NETX_GPIO_COUNTER_CTRL_IRQ_EN | NETX_GPIO_COUNTER_CTRL_RUN,
-		NETX_GPIO_COUNTER_CTRL(0));
+	       NETX_GPIO_COUNTER_CTRL(0));
 
 	setup_irq(NETX_IRQ_TIMER0, &netx_timer_irq);
 
 	/* Setup timer one for clocksource */
-        writel(0, NETX_GPIO_COUNTER_CTRL(1));
-        writel(0, NETX_GPIO_COUNTER_CURRENT(1));
-        writel(0xFFFFFFFF, NETX_GPIO_COUNTER_MAX(1));
+	writel(0, NETX_GPIO_COUNTER_CTRL(1));
+	writel(0, NETX_GPIO_COUNTER_CURRENT(1));
+	writel(0xFFFFFFFF, NETX_GPIO_COUNTER_MAX(1));
 
-        writel(NETX_GPIO_COUNTER_CTRL_RUN,
-                NETX_GPIO_COUNTER_CTRL(1));
+	writel(NETX_GPIO_COUNTER_CTRL_RUN,
+	       NETX_GPIO_COUNTER_CTRL(1));
 
 	clocksource_netx.mult =
 		clocksource_hz2mult(CLOCK_TICK_RATE, clocksource_netx.shift);
 	clocksource_register(&clocksource_netx);
+
+	clockevent_netx.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC,
+					clockevent_netx.shift);
+	clockevent_netx.max_delta_ns =
+		clockevent_delta2ns(0xfffffffe, &clockevent_netx);
+	clockevent_netx.min_delta_ns =
+		clockevent_delta2ns(0xf, &clockevent_netx);
+	register_local_clockevent(&clockevent_netx);
 }
 
 struct sys_timer netx_timer = {

Index: arch/arm/mach-pxa/time.c
===================================================================
@@ -19,6 +19,7 @@
 #include <linux/errno.h>
 #include <linux/sched.h>
 #include <linux/clocksource.h>
+#include <linux/clockchips.h>
 
 #include <asm/system.h>
 #include <asm/hardware.h>

@@ -29,6 +30,50 @@
 #include <asm/mach/time.h>
 #include <asm/arch/pxa-regs.h>
 
+static u32 clockevent_mode = 0;
+
+static void pxa_set_next_event(unsigned long evt,
+				  struct clock_event_device *unused)
+{
+	OSMR0 = OSCR + evt;
+}
+
+static void pxa_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
+{
+	switch (mode) {
+	case CLOCK_EVT_PERIODIC:
+	case CLOCK_EVT_ONESHOT:
+		OIER |= OIER_E0;
+		break;
+
+	case CLOCK_EVT_SHUTDOWN:
+		OIER &= ~OIER_E0;
+		return;
+	}
+	clockevent_mode = mode;
+}
+
+static struct clock_event_device clockevent_pxa = {
+	.name		= "pxa_timer1",
+	.capabilities	= CLOCK_CAP_NEXTEVT | CLOCK_CAP_TICK |
+			  CLOCK_CAP_UPDATE | CLOCK_CAP_PROFILE,
+	.shift		= 32,
+	.set_mode	= pxa_set_mode,
+	.set_next_event	= pxa_set_next_event,
+};
+
+static int __init pxa_clockevent_init(void)
+{
+	clockevent_pxa.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC,
+					clockevent_pxa.shift);
+	clockevent_pxa.max_delta_ns =
+		clockevent_delta2ns(0xfffffffe, &clockevent_pxa);
+	clockevent_pxa.min_delta_ns =
+		clockevent_delta2ns(0xf, &clockevent_pxa);
+	register_local_clockevent(&clockevent_pxa);
+
+	return 0;
+}
 
 static inline unsigned long pxa_get_rtc_time(void)
 {

@@ -49,25 +94,11 @@ static int pxa_set_rtc(void)
 	return 0;
 }
 
-#ifdef CONFIG_NO_IDLE_HZ
-static unsigned long initial_match;
-static int match_posponed;
-#endif
-
 static irqreturn_t
 pxa_timer_interrupt(int irq, void *dev_id)
 {
 	int next_match;
 
-	write_seqlock(&xtime_lock);
-
-#ifdef CONFIG_NO_IDLE_HZ
-	if (match_posponed) {
-		match_posponed = 0;
-		OSMR0 = initial_match;
-	}
-#endif
-
 	/* Loop until we get ahead of the free running timer.
 	 * This ensures an exact clock tick count and time accuracy.
 	 * Since IRQs are disabled at this point, coherence between

@@ -85,13 +116,15 @@ pxa_timer_interrupt(int irq, void *dev_i
 	 * exactly one tick period which should be a pretty rare event.
 	 */
 	do {
-		timer_tick();
+		clockevent_pxa.event_handler();
 		OSSR = OSSR_M0;  /* Clear match on timer 0 */
+
+		if (clockevent_mode != CLOCK_EVT_PERIODIC)
+			break;
+
 		next_match = (OSMR0 += LATCH);
 	} while( (signed long)(next_match - OSCR) <= 8 );
 
-	write_sequnlock(&xtime_lock);
-
 	return IRQ_HANDLED;
 }
 

@@ -141,44 +174,10 @@ static void __init pxa_timer_init(void)
 	clocksource_pxa.mult =
 		clocksource_hz2mult(CLOCK_TICK_RATE, clocksource_pxa.shift);
 	clocksource_register(&clocksource_pxa);
-}
-
-#ifdef CONFIG_NO_IDLE_HZ
-static int pxa_dyn_tick_enable_disable(void)
-{
-	/* nothing to do */
-	return 0;
-}
-
-static void pxa_dyn_tick_reprogram(unsigned long ticks)
-{
-	if (ticks > 1) {
-		initial_match = OSMR0;
-		OSMR0 = initial_match + ticks * LATCH;
-		match_posponed = 1;
-	}
-}
 
-static irqreturn_t
-pxa_dyn_tick_handler(int irq, void *dev_id)
-{
-	if (match_posponed) {
-		match_posponed = 0;
-		OSMR0 = initial_match;
-		if ( (signed long)(initial_match - OSCR) <= 8 )
-			return pxa_timer_interrupt(irq, dev_id);
-	}
-	return IRQ_NONE;
+	pxa_clockevent_init();
 }
 
-static struct dyn_tick_timer pxa_dyn_tick = {
-	.enable		= pxa_dyn_tick_enable_disable,
-	.disable	= pxa_dyn_tick_enable_disable,
-	.reprogram	= pxa_dyn_tick_reprogram,
-	.handler	= pxa_dyn_tick_handler,
-};
-#endif
-
 #ifdef CONFIG_PM
 static unsigned long osmr[4], oier;
 

@@ -213,7 +212,4 @@ struct sys_timer pxa_timer = {
 	.init		= pxa_timer_init,
 	.suspend	= pxa_timer_suspend,
 	.resume		= pxa_timer_resume,
-#ifdef CONFIG_NO_IDLE_HZ
-	.dyn_tick	= &pxa_dyn_tick,
-#endif
 };