Change the 82371SB PCI-to-ISA bridge into a 82371EB

PATCH In review Aurelien Jarno 3 participants 5 messages Jan 9, 2007 – Jan 11, 2007

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Aurelien Jarno

author

2007-01-09 15:44 UTC #0 lore raw

PATCH 1/1 Change the 82371SB PCI-to-ISA bridge into a 82371EB

This patch changes the 82371SB PCI-to-ISA bridge into a 82371EB. There are no differences in the implementation, but the Malta platform needs this device as there are some PCI fixup in the Linux kernel.

This should be supported without problem by the i386 and x86_64 targets as there is no standard PC hardware. Note that the ACPI controller implemented in QEMU is already a 82371EB.

hw/piix_pci.c +2 -2

diff -Nurd qemu/hw/piix_pci.c qemu/hw/piix_pci.c
@@ -287,8 +287,8 @@
 
     pci_conf[0x00] = 0x86; // Intel
     pci_conf[0x01] = 0x80;
-    pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
-    pci_conf[0x03] = 0x70;
+    pci_conf[0x02] = 0x10; // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge
+    pci_conf[0x03] = 0x71;
     pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
     pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
     pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic

Signature · 4 lines

  .''`.  Aurelien Jarno	            | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
 `. `'   [email protected]         | [email protected]
   `-    people.debian.org/~aurel32 | www.aurel32.net

Alexander Voropay

2007-01-09 18:01 UTC #1 lore raw

Re: [Qemu-devel] [PATCH] Change the 82371SB PCI-to-ISA bridge into a82371EB

Quoted 3 lines · Aurelien Jarno

This patch changes the 82371SB PCI-to-ISA bridge into a 82371EB.
Note that the ACPI controller implemented in QEMU is already a 82371EB.

Shouldn't we also change all "piix3" names to "piix4" ?

[qemu]$ find . -type f | xargs grep "piix3" | wc -l 18

--
-=AV=-

Aurelien Jarno

author

2007-01-10 00:54 UTC #2 lore raw

Re: [Qemu-devel] [PATCH] Change the 82371SB PCI-to-ISA bridge into a82371EB

Quoted 4 lines · Alexander Voropay

Quoted 2 lines · Aurelien Jarno
This patch changes the 82371SB PCI-to-ISA bridge into a 82371EB.

Quoted 9 lines

Quoted 2 lines
Note that the ACPI controller
implemented in QEMU is already a 82371EB.
Shouldn't we also change all "piix3" names to "piix4" ?
[qemu]$ find . -type f | xargs grep "piix3" | wc -l 18

You are probably right for this device, but note that the USB and the IDE controller are still PIIX3. And this corresponds to the emulated devices. Ideally it would be nice to also change them into PIIX4 by implementing the missing features. Some of the missing features are really cool, like DMA support in IDE controller.

Please find below a new patch that also changes the name of the ISA bridge to piix4. That introduces a sequence in the patches, it needs to be applied after the patch "devfn number for the PIIX3 southbridge".

Bye,
Aurelien

This should be supported without problem by the i386 and x86_64 targets as there is no standard PC hardware. Note that the ACPI controller implemented in QEMU is already a 82371EB.

hw/pc.c +5 -5

diff -Nurd qemu.orig/hw/pc.c qemu/hw/pc.c
@@ -454,7 +454,7 @@
     unsigned long bios_offset, vga_bios_offset, option_rom_offset;
     int bios_size, isa_bios_size;
     PCIBus *pci_bus;
-    int piix3_devfn = -1;
+    int piix4_devfn = -1;
     CPUState *env;
     NICInfo *nd;

@@ -599,7 +599,7 @@
 
     if (pci_enabled) {
         pci_bus = i440fx_init(&i440fx_state);
-        piix3_devfn = piix3_init(pci_bus, -1);
+        piix4_devfn = piix4_init(pci_bus, -1);
     } else {
         pci_bus = NULL;
     }

@@ -676,7 +676,7 @@
     }
 
     if (pci_enabled) {
-        pci_piix3_ide_init(pci_bus, bs_table, piix3_devfn + 1);
+        pci_piix3_ide_init(pci_bus, bs_table, piix4_devfn + 1);
     } else {
         for(i = 0; i < 2; i++) {
             isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],

@@ -695,11 +695,11 @@
     cmos_init(ram_size, boot_device, bs_table);
 
     if (pci_enabled && usb_enabled) {
-        usb_uhci_init(pci_bus, piix3_devfn + 2);
+        usb_uhci_init(pci_bus, piix4_devfn + 2);
     }
 
     if (pci_enabled && acpi_enabled) {
-        piix4_pm_init(pci_bus, piix3_devfn + 3);
+        piix4_pm_init(pci_bus, piix4_devfn + 3);
     }
     
     if (i440fx_state) {

hw/piix_pci.c +14 ~~-14~~

diff -Nurd qemu.orig/hw/piix_pci.c qemu/hw/piix_pci.c
@@ -40,7 +40,7 @@
     return s->config_reg;
 }
 
-static void piix3_set_irq(void *pic, int irq_num, int level);
+static void piix4_set_irq(void *pic, int irq_num, int level);
 
 /* return the global irq number corresponding to a given device irq
    pin. We could also use the bus number to have a more precise

@@ -162,7 +162,7 @@
     I440FXState *s;
 
     s = qemu_mallocz(sizeof(I440FXState));
-    b = pci_register_bus(piix3_set_irq, pci_slot_get_pirq, NULL, 0, 4);
+    b = pci_register_bus(piix4_set_irq, pci_slot_get_pirq, NULL, 0, 4);
     s->bus = b;
 
     register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);

@@ -196,14 +196,14 @@
 
 /* PIIX3 PCI to ISA bridge */
 
-PCIDevice *piix3_dev;
+PCIDevice *piix4_dev;
 
 /* just used for simpler irq handling. */
 #define PCI_IRQ_WORDS   ((PCI_DEVICES_MAX + 31) / 32)
 
 static int pci_irq_levels[4];
 
-static void piix3_set_irq(void *pic, int irq_num, int level)
+static void piix4_set_irq(void *pic, int irq_num, int level)
 {
     int i, pic_irq, pic_level;

@@ -211,20 +211,20 @@
 
     /* now we change the pic irq level according to the piix irq mappings */
     /* XXX: optimize */
-    pic_irq = piix3_dev->config[0x60 + irq_num];
+    pic_irq = piix4_dev->config[0x60 + irq_num];
     if (pic_irq < 16) {
         /* The pic level is the logical OR of all the PCI irqs mapped
            to it */
         pic_level = 0;
         for (i = 0; i < 4; i++) {
-            if (pic_irq == piix3_dev->config[0x60 + i])
+            if (pic_irq == piix4_dev->config[0x60 + i])
                 pic_level |= pci_irq_levels[i];
         }
         pic_set_irq(pic_irq, pic_level);
     }
 }
 
-static void piix3_reset(PCIDevice *d)
+static void piix4_reset(PCIDevice *d)
 {
     uint8_t *pci_conf = d->config;

@@ -273,26 +273,26 @@
     return pci_device_load(d, f);
 }
 
-int piix3_init(PCIBus *bus, int devfn)
+int piix4_init(PCIBus *bus, int devfn)
 {
     PCIDevice *d;
     uint8_t *pci_conf;
 
-    d = pci_register_device(bus, "PIIX3", sizeof(PCIDevice),
+    d = pci_register_device(bus, "PIIX4", sizeof(PCIDevice),
                                     devfn, NULL, NULL);
-    register_savevm("PIIX3", 0, 2, piix_save, piix_load, d);
+    register_savevm("PIIX4", 0, 2, piix_save, piix_load, d);
 
-    piix3_dev = d;
+    piix4_dev = d;
     pci_conf = d->config;
 
     pci_conf[0x00] = 0x86; // Intel
     pci_conf[0x01] = 0x80;
-    pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
-    pci_conf[0x03] = 0x70;
+    pci_conf[0x02] = 0x10; // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge
+    pci_conf[0x03] = 0x71;
     pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
     pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
     pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
 
-    piix3_reset(d);
+    piix4_reset(d);
     return d->devfn;
 }

vl.h +1 -1

diff -Nurd qemu.orig/vl.h qemu/vl.h
@@ -821,7 +821,7 @@
 /* piix_pci.c */
 PCIBus *i440fx_init(PCIDevice **pi440fx_state);
 void i440fx_set_smm(PCIDevice *d, int val);
-int piix3_init(PCIBus *bus, int devfn);
+int piix4_init(PCIBus *bus, int devfn);
 void i440fx_init_memory_mappings(PCIDevice *d);
 
 /* openpic.c */

Signature · 4 lines

  .''`.  Aurelien Jarno	            | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
 `. `'   [email protected]         | [email protected]
   `-    people.debian.org/~aurel32 | www.aurel32.net

Fabrice Bellard

2007-01-11 20:10 UTC #3 lore raw

Re: [Qemu-devel] [PATCH] Change the 82371SB PCI-to-ISA bridge into a82371EB

I would prefer to keep the PIIX3 for the PC until the PIIX4 is more tested (and implemented !). I would accept having both PIIX3 and PIIX4 (a flag could suffice at the init).

Regards,

Fabrice.

Quoted 38 lines · Aurelien Jarno

Quoted 13 lines · Alexander Voropay
Quoted 3 lines · Aurelien Jarno
This patch changes the 82371SB PCI-to-ISA bridge into a 82371EB.
Note that the ACPI controller implemented in QEMU is already a 82371EB.
Shouldn't we also change all "piix3" names to "piix4" ?
[qemu]$ find . -type f | xargs grep "piix3" | wc -l 18
You are probably right for this device, but note that the USB and the IDE controller are still PIIX3. And this corresponds to the emulated devices. Ideally it would be nice to also change them into PIIX4 by implementing the missing features. Some of the missing features are really cool, like DMA support in IDE controller.
Please find below a new patch that also changes the name of the ISA bridge to piix4. That introduces a sequence in the patches, it needs to be applied after the patch "devfn number for the PIIX3 southbridge".
Bye,
Aurelien
This patch changes the 82371SB PCI-to-ISA bridge into a 82371EB. There
are no differences in the implementation, but the Malta platform needs this device as there are some PCI fixup in the Linux kernel.
This should be supported without problem by the i386 and x86_64 targets
as there is no standard PC hardware. Note that the ACPI controller implemented in QEMU is already a 82371EB. [...]

Aurelien Jarno

author

2007-01-11 22:13 UTC #4 lore raw

Re: [Qemu-devel] [PATCH] Change the 82371SB PCI-to-ISA bridge into a82371EB

Quoted 4 lines · Fabrice Bellard

I would prefer to keep the PIIX3 for the PC until the PIIX4 is more tested (and implemented !). I would accept having both PIIX3 and PIIX4 (a flag could suffice at the init).

Please find below a new patch. I have actually implemented it by copying the code, as I have found after sedning the previous one that some other PCI registers should have different values. That's currently the case of the PCI IRQ routing registers (0x60 to 0x63) and maybe some other registers in the future.

Cheers,
Aurelien

This patch adds the 82371EB PCI-to-ISA bridge. This device is needed for the Malta platform and cannot be replaced by the 82371SB as there are some specific PCI fixups in the Linux kernel. However there are very few differences with the 82371SB, so this device could eventually be used for the i386 and x86_64 targets. Note however that the PCI IRQ are not routed exactly the same way, but that should not hurt the later platforms.

hw/piix_pci.c +63 -0

diff -Nurd qemu.orig/hw/piix_pci.c qemu/hw/piix_pci.c
@@ -197,6 +197,7 @@ PCIBus *i440fx_init(PCIDevice **pi440fx_
 /* PIIX3 PCI to ISA bridge */
 
 PCIDevice *piix3_dev;
+PCIDevice *piix4_dev;
 
 /* just used for simpler irq handling. */
 #define PCI_IRQ_WORDS   ((PCI_DEVICES_MAX + 31) / 32)

@@ -259,6 +260,44 @@ static void piix3_reset(PCIDevice *d)
     pci_conf[0xae] = 0x00;
 }
 
+static void piix4_reset(PCIDevice *d)
+{
+    uint8_t *pci_conf = d->config;
+
+    pci_conf[0x04] = 0x07; // master, memory and I/O
+    pci_conf[0x05] = 0x00;
+    pci_conf[0x06] = 0x00;
+    pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
+    pci_conf[0x4c] = 0x4d;
+    pci_conf[0x4e] = 0x03;
+    pci_conf[0x4f] = 0x00;
+    pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
+    pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
+    pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
+    pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
+    pci_conf[0x69] = 0x02;
+    pci_conf[0x70] = 0x80;
+    pci_conf[0x76] = 0x0c;
+    pci_conf[0x77] = 0x0c;
+    pci_conf[0x78] = 0x02;
+    pci_conf[0x79] = 0x00;
+    pci_conf[0x80] = 0x00;
+    pci_conf[0x82] = 0x00;
+    pci_conf[0xa0] = 0x08;
+    pci_conf[0xa0] = 0x08;
+    pci_conf[0xa2] = 0x00;
+    pci_conf[0xa3] = 0x00;
+    pci_conf[0xa4] = 0x00;
+    pci_conf[0xa5] = 0x00;
+    pci_conf[0xa6] = 0x00;
+    pci_conf[0xa7] = 0x00;
+    pci_conf[0xa8] = 0x0f;
+    pci_conf[0xaa] = 0x00;
+    pci_conf[0xab] = 0x00;
+    pci_conf[0xac] = 0x00;
+    pci_conf[0xae] = 0x00;
+}
+
 static void piix_save(QEMUFile* f, void *opaque)
 {
     PCIDevice *d = opaque;

@@ -296,3 +335,27 @@ int piix3_init(PCIBus *bus, int devfn)
     piix3_reset(d);
     return d->devfn;
 }
+
+int piix4_init(PCIBus *bus, int devfn)
+{
+    PCIDevice *d;
+    uint8_t *pci_conf;
+
+    d = pci_register_device(bus, "PIIX4", sizeof(PCIDevice),
+                                    devfn, NULL, NULL);
+    register_savevm("PIIX4", 0, 2, piix_save, piix_load, d);
+
+    piix4_dev = d;
+    pci_conf = d->config;
+
+    pci_conf[0x00] = 0x86; // Intel
+    pci_conf[0x01] = 0x80;
+    pci_conf[0x02] = 0x10; // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge
+    pci_conf[0x03] = 0x71;
+    pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
+    pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
+    pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
+
+    piix4_reset(d);
+    return d->devfn;
+}

Signature · 4 lines

  .''`.  Aurelien Jarno	            | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
 `. `'   [email protected]         | [email protected]
   `-    people.debian.org/~aurel32 | www.aurel32.net