atyfb: Increase SPLL delay
PATCH 1/1 atyfb: Increase SPLL delay
Wait 5 ms instead of 500 us for the SPLL to lock. This matches the recommendation in mach64 programmer's guide.
Signed-off-by Ville Syrjala <[email protected]>
--- drivers/video/aty/mach64_ct.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-)
drivers/video/aty/mach64_ct.c +3 -5
@@ -608,12 +608,10 @@ static void aty_resume_pll_ct(const struaty_st_pll_ct (SCLK_FB_DIV , pll->ct.sclk_fb_div, par);aty_st_pll_ct (SPLL_CNTL2 , pll->ct.spll_cntl2, par);/* -* The sclk has been started. However, I believe the first clock -* ticks it generates are not very stable. Hope this primitive loop -* helps for Rage Mobilities that sometimes crash when -* we switch to sclk. (Daniel Mantione, 13-05-2003) +* SCLK has been started. Wait for the PLL to lock. 5 ms +* should be enough according to mach64 programmer's guide. */ -udelay (500 ); +mdelay (5 ); }aty_st_pll_ct (PLL_REF_DIV , pll->ct.pll_ref_div, par);
Signature · 9 lines
Ville Syrjälä [email protected] http://www.sci.fi/~syrjala/ ------------------------------------------------------------------------- Take Surveys. Earn Cash. Influence the Future of IT Join SourceForge.net's Techsay panel and you'll get the chance to share your opinions on IT & business topics through brief surveys-and earn cash http://www.techsay.com/default.php?page=join.php&p=sourceforge&CID=DEVDEV