Cleanup for plat_irq_dispatch functions
PATCH 1/1 Cleanup for plat_irq_dispatch functions
Hello All,
the appended patch
- adds missing ST0_IM masks, which caused the logging of valid interrupts as spurious
- stops pnx8550 to log every interrupt as spurious
- adds cause register masks for ip22/ip32, which caused handling of masked interrupts
- removes some superfluous parentheses in the SNI interrupt code
Thiemo
arch/mips/ddb5xxx/ddb5477/irq.c +1 -1
@@ -194,7 +194,7 @@ static void vrc5477_irq_dispatch(void) asmlinkage void plat_irq_dispatch(void) { -unsigned int pending =read_c0_cause () &read_c0_status (); +unsigned int pending =read_c0_cause () &read_c0_status () &ST0_IM ;if (pending &STATUSF_IP7 )do_IRQ (CPU_IRQ_BASE +7 );
arch/mips/emma2rh/markeins/irq.c +1 -1
@@ -115,7 +115,7 @@ void __init arch_init_irq(void) asmlinkage void plat_irq_dispatch(void) { -unsigned int pending =read_c0_status () &read_c0_cause (); +unsigned int pending =read_c0_status () &read_c0_cause () &ST0_IM ;if (pending &STATUSF_IP7 )do_IRQ (CPU_IRQ_BASE +7 );
arch/mips/gt64120/ev64120/irq.c +1 -1
@@ -48,7 +48,7 @@ asmlinkage void plat_irq_dispatch(void) { -unsigned int pending =read_c0_status () &read_c0_cause (); +unsigned int pending =read_c0_status () &read_c0_cause () &ST0_IM ;if (pending &STATUSF_IP4 )/* int2 hardware line (timer) */ do_IRQ (4 );
arch/mips/gt64120/wrppmc/irq.c +1 -1
@@ -32,7 +32,7 @@ asmlinkage void plat_irq_dispatch(void) { -unsigned int pending =read_c0_status () &read_c0_cause (); +unsigned int pending =read_c0_status () &read_c0_cause () &ST0_IM ;if (pending &STATUSF_IP7 )do_IRQ (WRPPMC_MIPS_TIMER_IRQ );/* CPU Compare/Count internal timer */
arch/mips/jazz/irq.c +1 -1
@@ -122,7 +122,7 @@ static void ll_local_dev(void) asmlinkage void plat_irq_dispatch(void) { -unsigned int pending =read_c0_cause () &read_c0_status () &ST0_IM ; +unsigned int pending =read_c0_cause () &read_c0_status ();if (pending &IE_IRQ5 )write_c0_compare (0 );
arch/mips/momentum/ocelot_c/irq.c +1 -1
@@ -64,7 +64,7 @@ extern void ll_cpci_irq(void); asmlinkage void plat_irq_dispatch(void) { -unsigned int pending =read_c0_cause () &read_c0_status (); +unsigned int pending =read_c0_cause () &read_c0_status () &ST0_IM ;if (pending &STATUSF_IP0 )do_IRQ (0 );
arch/mips/philips/pnx8550/common/int.c +3 -4
@@ -83,16 +83,15 @@ static void timer_irqdispatch(int irq) asmlinkage void plat_irq_dispatch(void) { -unsigned int pending =read_c0_status () &read_c0_cause (); +unsigned int pending =read_c0_status () &read_c0_cause () &ST0_IM ;if (pending &STATUSF_IP2 )hw0_irqdispatch (2 );else if (pending &STATUSF_IP7 ) {if (read_c0_config7 () &0x01c0 )timer_irqdispatch (7 ); - } - -spurious_interrupt (); + }else +spurious_interrupt (); }static inline void modify_cp0_intmask (unsigned clr_mask,unsigned set_mask)
arch/mips/sgi-ip22/ip22-int.c +1 -1
@@ -237,7 +237,7 @@ extern void indy_8254timer_irq(void); asmlinkage void plat_irq_dispatch(void) { -unsigned int pending =read_c0_cause (); +unsigned int pending =read_c0_status () &read_c0_cause ();/* * First we check for r4k counter/timer IRQ.
arch/mips/sgi-ip32/ip32-irq.c +1 -1
@@ -454,7 +454,7 @@ static void ip32_irq5(void) asmlinkage void plat_irq_dispatch(void) { -unsigned int pending =read_c0_cause (); +unsigned int pending =read_c0_status () &read_c0_cause ();if (likely (pending &IE_IRQ0 ))ip32_irq0 ();
arch/mips/sibyte/sb1250/irq.c +1 -1
@@ -421,7 +421,7 @@ asmlinkage void plat_irq_dispatch(void)* blasting the high 32 bits. */ - pending =read_c0_cause () &read_c0_status (); + pending =read_c0_cause () &read_c0_status () &ST0_IM ;#ifdef CONFIG_SIBYTE_SB1250_PROF if (pending &CAUSEF_IP7 )/* Cpu performance counter interrupt */
arch/mips/sni/pcimt.c +1 -1
@@ -333,7 +333,7 @@ static void pcimt_hwint3(void)static void sni_pcimt_hwint (void ) { -u32 pending = (read_c0_cause () &read_c0_status ()); +u32 pending =read_c0_cause () &read_c0_status ();if (pending &C_IRQ5 )do_IRQ (MIPS_CPU_IRQ_BASE +7 );
arch/mips/sni/pcit.c +2 -2
@@ -271,7 +271,7 @@ static void pcit_hwint0(void)static void sni_pcit_hwint (void ) { -u32 pending = (read_c0_cause () &read_c0_status ()); +u32 pending =read_c0_cause () &read_c0_status ();if (pending &C_IRQ1 )pcit_hwint1 ();
@@ -285,7 +285,7 @@ static void sni_pcit_hwint(void)static void sni_pcit_hwint_cplus (void ) { -u32 pending = (read_c0_cause () &read_c0_status ()); +u32 pending =read_c0_cause () &read_c0_status ();if (pending &C_IRQ0 )pcit_hwint0 ();
arch/mips/tx4927/common/tx4927_irq.c +1 -1
@@ -416,7 +416,7 @@ static int tx4927_irq_nested(void) asmlinkage void plat_irq_dispatch(void) { -unsigned int pending =read_c0_status () &read_c0_cause (); +unsigned int pending =read_c0_status () &read_c0_cause () &ST0_IM ;if (pending &STATUSF_IP7 )/* cpu timer */ do_IRQ (TX4927_IRQ_CPU_TIMER );
Quoted 7 lines · Thiemo Seufer
the appended patch
- adds missingST0_IMmasks, which caused the logging of valid interrupts as spurious
- stops pnx8550 to log every interrupt as spurious
- adds cause register masks for ip22/ip32, which caused handling of masked interrupts
- removes some superfluous parentheses in the SNI interrupt code
Thanks for sorting this out.
Now, I think spurious_interrupt should be deleted, it delivers not too much useful data and even the reasoning for adding it back in the dark ages was fairly weak ...
Ralf
Quoted 3 lines · Ralf Baechle
Now, I think
spurious_interruptshould be deleted, it delivers not too much useful data and even the reasoning for adding it back in the dark ages was fairly weak ...
It is useful for debugging -- if you get more than a few such events in a
long time, then you need to debug your driver to make sure the interrupt request is removed soon enough for not being redelivered when the handler exits. The problem is hard to notice otherwise.
Maciej