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ppc: Add support for AMCC 440EPx and 440GRx PPC's

PATCH New Stefan Roese 1 participant 1 message Mar 26, 2007 PowerPC

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Stefan Roese

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PATCH 1/4 ppc: Add support for AMCC 440EPx and 440GRx PPC's

This patch adds initial support for the AMCC 440EPx/440GRx PPC's. It's in preparation for adding support for the AMCC eval boards Sequoia (440EPx) and Rainier (440GRx).

Signed-off-by Stefan Roese <[email protected]>

---
commit 7a62196fb100073aebe46487160da1aa0e9b3c9e
tree 20345010893b44457d5285b65781fd04cf744bae
parent f33bc55c472295966e520c9347822fdd8b1082cd
author Stefan Roese <[email protected]> Mon, 26 Mar 2007 08:58:33 +0200 committer Stefan Roese <[email protected]> Mon, 26 Mar 2007 08:58:33 +0200

 arch/powerpc/kernel/cputable.c     |   40 +++++
 arch/ppc/kernel/head_44x.S         |    2 
 arch/ppc/platforms/4xx/Kconfig     |   34 ++++
 arch/ppc/platforms/4xx/Makefile    |    4 
 arch/ppc/platforms/4xx/ppc440epx.c |  289 ++++++++++++++++++++++++++++++++++++
 arch/ppc/platforms/4xx/ppc440epx.h |   85 +++++++++++
 arch/ppc/syslib/Makefile           |    4 
 arch/ppc/syslib/ibm44x_common.c    |   24 +++
 arch/ppc/syslib/ibm44x_common.h    |    3 
 arch/ppc/syslib/ppc4xx_pic.c       |   30 ++++
 include/asm-ppc/ibm44x.h           |  120 +++++++++++++--
 include/asm-ppc/ibm4xx.h           |    4 
 include/asm-ppc/ibm_ocp.h          |    7 +
 13 files changed, 627 insertions(+), 19 deletions(-)
arch/powerpc/kernel/cputable.c +40 -0
index e4006dc..e0587e8 100644
@@ -1179,6 +1179,46 @@ static struct cpu_spec cpu_specs[] = {
 		.dcache_bsize		= 32,
 		.platform		= "ppc440",
 	},
+	{ /* 440EPx - with Security/Kasumi */
+		.pvr_mask		= 0xf0000fff,
+		.pvr_value		= 0x200008D0,
+		.cpu_name		= "440EPx - with Security/Kasumi",
+		.cpu_features           = CPU_FTRS_44X,
+		.cpu_user_features      = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
+		.icache_bsize		= 32,
+		.dcache_bsize		= 32,
+		.platform		= "ppc440",
+	},
+	{ /* 440EPx - without Security/Kasumi */
+		.pvr_mask		= 0xf0000fff,
+		.pvr_value		= 0x200008D4,
+		.cpu_name		= "440EPx - no Security/Kasumi",
+		.cpu_features           = CPU_FTRS_44X,
+		.cpu_user_features      = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
+		.icache_bsize		= 32,
+		.dcache_bsize		= 32,
+		.platform		= "ppc440",
+	},
+	{ /* 440GRx - with Security/Kasumi */
+		.pvr_mask		= 0xf0000fff,
+		.pvr_value		= 0x200008D8,
+		.cpu_name		= "440GRx - with Security/Kasumi",
+		.cpu_features		= CPU_FTRS_44X,
+		.cpu_user_features	= COMMON_USER_BOOKE,
+		.icache_bsize		= 32,
+		.dcache_bsize		= 32,
+		.platform		= "ppc440",
+	},
+	{ /* 440GRx - without Security/Kasumi */
+		.pvr_mask		= 0xf0000fff,
+		.pvr_value		= 0x200008DC,
+		.cpu_name		= "440GRx - no Security/Kasumi",
+		.cpu_features		= CPU_FTRS_44X,
+		.cpu_user_features	= COMMON_USER_BOOKE,
+		.icache_bsize		= 32,
+		.dcache_bsize		= 32,
+		.platform		= "ppc440",
+	},
 #endif /* CONFIG_44x */
 #ifdef CONFIG_FSL_BOOKE
 	{	/* e200z5 */
arch/ppc/kernel/head_44x.S +1 -1
index 7e44de5..17a6243 100644
@@ -227,7 +227,7 @@ skpinv:	addi	r4,r4,1				/* Increment */
 	lis	r4,interrupt_base@h	/* IVPR only uses the high 16-bits */
 	mtspr	SPRN_IVPR,r4
 
-#ifdef CONFIG_440EP
+#if defined(CONFIG_440EP) || defined(CONFIG_440EPX)
 	/* Clear DAPUIB flag in CCR0 (enable APU between CPU and FPU) */
 	mfspr	r2,SPRN_CCR0
 	lis	r3,0xffef
arch/ppc/platforms/4xx/Kconfig +31 -3
index 705ae56..1d42ecc 100644
@@ -98,6 +98,18 @@ config OCOTEA
 	help
 	  This option enables support for the IBM PPC440GX evaluation board.
 
+config RAINIER
+	bool "Rainier"
+	select WANT_EARLY_SERIAL
+	help
+	  This option enables support for the AMCC PPC440GRx evaluation board.
+
+config SEQUOIA
+	bool "Sequoia"
+	select WANT_EARLY_SERIAL
+	help
+	  This option enables support for the AMCC PPC440EPx evaluation board.
+
 config TAISHAN
 	bool "Taishan"
 	select WANT_EARLY_SERIAL

@@ -125,11 +137,22 @@ config 440EP
 	select PPC_FPU
 	default y
 
+config 440EPX
+	bool
+	depends on SEQUOIA
+	select PPC_FPU
+	default y
+
 config 440GP
 	bool
 	depends on EBONY
 	default y
 
+config 440GRX
+	bool
+	depends on RAINIER
+	default y
+
 config 440GX
 	bool
 	depends on OCOTEA || TAISHAN

@@ -152,7 +175,7 @@ config 440
 
 config 440A
 	bool
-	depends on 440GX
+	depends on 440GX || 440EPX || 440GRX
 	default y
 
 config IBM440EP_ERR42

@@ -179,12 +202,17 @@ config BOOKE
 
 config IBM_OCP
 	bool
-	depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || TAISHAN || WALNUT
+	depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || RAINIER || REDWOOD_5 || REDWOOD_6 || SEQUOIA || SYCAMORE || TAISHAN || WALNUT
 	default y
 
 config IBM_EMAC4
 	bool
-	depends on 440GX || 440SP || 440SPE
+	depends on 440EPX || 440GRX || 440GX || 440SP || 440SPE
+	default y
+
+config IBM_EMAC4V4
+	bool
+	depends on 440EPX || 440GRX
 	default y
 
 config BIOS_FIXUP
arch/ppc/platforms/4xx/Makefile +4 -0
index fa6610b..a91c604 100644
@@ -9,8 +9,10 @@ obj-$(CONFIG_BUBINGA)		+= bubinga.o
 obj-$(CONFIG_LUAN)		+= luan.o
 obj-$(CONFIG_YUCCA)		+= yucca.o
 obj-$(CONFIG_OCOTEA)		+= ocotea.o
+obj-$(CONFIG_RAINIER)		+= sequoia.o
 obj-$(CONFIG_REDWOOD_5)		+= redwood5.o
 obj-$(CONFIG_REDWOOD_6)		+= redwood6.o
+obj-$(CONFIG_SEQUOIA)		+= sequoia.o
 obj-$(CONFIG_SYCAMORE)		+= sycamore.o
 obj-$(CONFIG_TAISHAN)		+= taishan.o
 obj-$(CONFIG_WALNUT)		+= walnut.o

@@ -22,7 +24,9 @@ obj-$(CONFIG_REDWOOD_5)		+= ibmstb4.o
 obj-$(CONFIG_NP405H)		+= ibmnp405h.o
 obj-$(CONFIG_REDWOOD_6)		+= ibmstbx25.o
 obj-$(CONFIG_440EP)		+= ibm440ep.o
+obj-$(CONFIG_440EPX)		+= ppc440epx.o
 obj-$(CONFIG_440GP)		+= ibm440gp.o
+obj-$(CONFIG_440GRX)		+= ppc440epx.o
 obj-$(CONFIG_440GX)		+= ibm440gx.o
 obj-$(CONFIG_440SP)		+= ibm440sp.o
 obj-$(CONFIG_440SPE)		+= ppc440spe.o
arch/ppc/platforms/4xx/ppc440epx.c new file +289 -0

289 lines not on this page · raw message

arch/ppc/platforms/4xx/ppc440epx.h new file +85 -0

85 lines not on this page · raw message

arch/ppc/syslib/Makefile +4 -0
index 0991111..553417c 100644
@@ -12,7 +12,9 @@ obj-$(CONFIG_PPC_OCP)		+= ocp.o
 obj-$(CONFIG_IBM_OCP)		+= ibm_ocp.o
 obj-$(CONFIG_44x)		+= ibm44x_common.o
 obj-$(CONFIG_440EP)		+= ibm440gx_common.o
+obj-$(CONFIG_440EPX)		+= ibm440gx_common.o
 obj-$(CONFIG_440GP)		+= ibm440gp_common.o
+obj-$(CONFIG_440GRX)		+= ibm440gx_common.o
 obj-$(CONFIG_440GX)		+= ibm440gx_common.o
 obj-$(CONFIG_440SP)		+= ibm440gx_common.o ibm440sp_common.o
 obj-$(CONFIG_440SPE)		+= ibm440gx_common.o ibm440sp_common.o ppc440spe_pcie.o

@@ -65,8 +67,10 @@ obj-$(CONFIG_PRPMC750)		+= open_pic.o pci_auto.o \
 obj-$(CONFIG_HARRIER)		+= harrier.o
 obj-$(CONFIG_PRPMC800)		+= open_pic.o pci_auto.o
 obj-$(CONFIG_RADSTONE_PPC7D)	+= pci_auto.o
+obj-$(CONFIG_RAINIER)		+= pci_auto.o
 obj-$(CONFIG_SANDPOINT)		+= pci_auto.o todc_time.o
 obj-$(CONFIG_SBC82xx)		+= todc_time.o
+obj-$(CONFIG_SEQUOIA)		+= pci_auto.o
 obj-$(CONFIG_SPRUCE)		+= cpc700_pic.o pci_auto.o \
 				   todc_time.o
 obj-$(CONFIG_TAISHAN)		+= pci_auto.o
arch/ppc/syslib/ibm44x_common.c +24 -0
index 01f99b4..555d83c 100644
@@ -221,6 +221,30 @@ void platform_machine_check(struct pt_regs *regs)
 	       mfdcr(DCRN_PLB1_BEARH), mfdcr(DCRN_PLB1_BEARL),
 	       mfdcr(DCRN_PLB1_ACR), mfdcr(DCRN_PLB1_BESRH),
 	       mfdcr(DCRN_PLB1_BESRL));
+#elif defined(CONFIG_440EPX)|| defined(CONFIG_440GRX)
+     	printk("OPB to PLB3: BSTAT= 0x%08x\n",
+	       mfdcr(DCRN_OPB2PLB30_BSTAT));
+	printk("PLB3 to PLB4: BEAR=0x%08x%08x BESR0=0x%08x BESR1=0x%08x\n",
+	       mfdcr(DCRN_P3P4BI0_BEARH), mfdcr(DCRN_P3P4BI0_BEARL),
+	       mfdcr(DCRN_P3P4BI0_BESR0), mfdcr(DCRN_P3P4BI0_BESR1));
+	printk("PLB4 to PLB3: BEAR=0x%08x%08x BESR0=0x%08x BESR1=0x%08x\n",
+	       mfdcr(DCRN_P4P3BO0_BEARH), mfdcr(DCRN_P4P3BO0_BEARL),
+	       mfdcr(DCRN_P4P3BO0_BESR0), mfdcr(DCRN_P4P3BO0_BESR1));
+	printk("PLB3 to OPB: BEAR=0x%08x BESR0=0x%08x BESR1=0x%08x\n",
+	       mfdcr(DCRN_PLB32OPB0_BEAR),
+	       mfdcr(DCRN_PLB32OPB0_BESR0), mfdcr(DCRN_PLB32OPB0_BESR1));
+	printk("PLB3 arbiter: BEAR=0x%08x ACR=0x%08x BESR=0x%08x\n",
+	       mfdcr(DCRN_PLB3A0_BEAR),
+	       mfdcr(DCRN_PLB3A0_ACR),  mfdcr(DCRN_PLB3A0_BESR));
+	printk("PLB4 to OPB1: BEAR=0x%08x%08x BESR0=0x%08x BESR1=0x%08x\n",
+	       mfdcr(DCRN_PLB42OPB1_BEARH), mfdcr(DCRN_PLB42OPB1_BEARL),
+	       mfdcr(DCRN_PLB42OPB1_BESR0), mfdcr(DCRN_PLB42OPB1_BESR1));
+	printk("PLB40 Arbiter: BEAR=0x%08x%08x ACR=0x%08x BESR0=0x%08x\n",
+	       mfdcr(DCRN_PLB4A0_BEARH), mfdcr(DCRN_PLB4A0_BEARL),
+	       mfdcr(DCRN_PLB4A0_ACR), mfdcr(DCRN_PLB4A0_BESR));
+	printk("PLB41 Arbiter: BEAR=0x%08x%08x ACR=0x%08x BESR0=0x%08x\n",
+	       mfdcr(DCRN_PLB4A1_BEARH), mfdcr(DCRN_PLB4A1_BEARL),
+	       mfdcr(DCRN_PLB4A1_ACR), mfdcr(DCRN_PLB4A1_BESR));
 #else
     	printk("PLB0: BEAR=0x%08x%08x ACR=  0x%08x BESR= 0x%08x\n",
 		mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL),
arch/ppc/syslib/ibm44x_common.h +2 -1
index f179db8..5fb0e18 100644
@@ -27,7 +27,8 @@ struct ibm44x_clocks {
 	unsigned int ebc;	/* PerClk */
 	unsigned int uart0;
 	unsigned int uart1;
-#ifdef CONFIG_440EP
+#if defined(CONFIG_440EP) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	unsigned int uart2;
 	unsigned int uart3;
 #endif
arch/ppc/syslib/ppc4xx_pic.c +30 -0
index ee0da4b..0e5b2aa 100644
@@ -118,6 +118,35 @@ static void __init ppc4xx_pic_impl_init(void)
 }
 
 #elif NR_UICS == 3
+#if defined(CONFIG_440EPX)|| defined(CONFIG_440GRX)
+#define ACK_UIC0_PARENT
+#define ACK_UIC1_PARENT	mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC);
+#define ACK_UIC2_PARENT	mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC2NC);
+UIC_HANDLERS(0);
+UIC_HANDLERS(1);
+UIC_HANDLERS(2);
+
+static int ppc4xx_pic_get_irq(struct pt_regs *regs)
+{
+	u32 uic0 = mfdcr(DCRN_UIC_MSR(UIC0));
+	if (uic0 & UIC0_UIC1NC)
+		return 64 - ffs(mfdcr(DCRN_UIC_MSR(UIC1)));
+	else if (uic0 & UIC0_UIC2NC)
+		return 96 - ffs(mfdcr(DCRN_UIC_MSR(UIC2)));
+	else
+		return uic0 ? 32 - ffs(uic0) : -1;
+}
+
+static void __init ppc4xx_pic_impl_init(void)
+{
+	/* Enable cascade interrupts in UIC0 */
+	ppc_cached_irq_mask[0] |= UIC0_UIC1NC | UIC0_UIC2NC;
+	mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC | UIC0_UIC2NC );
+	mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]);
+}
+
+#else /* #if defined(CONFIG_440EPX)|| defined(CONFIG_440GRX) */
+
 #define ACK_UIC0_PARENT	mtdcr(DCRN_UIC_SR(UICB), UICB_UIC0NC);
 #define ACK_UIC1_PARENT	mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC);
 #define ACK_UIC2_PARENT	mtdcr(DCRN_UIC_SR(UICB), UICB_UIC2NC);

@@ -152,6 +181,7 @@ static void __init ppc4xx_pic_impl_init(void)
 	mtdcr(DCRN_UIC_ER(UICB), UICB_UIC0NC | UICB_UIC1NC | UICB_UIC2NC);
 }
 
+#endif /* #if defined(CONFIG_440EPX)|| defined(CONFIG_440GRX) */
 #elif NR_UICS == 2
 #define ACK_UIC0_PARENT
 #define ACK_UIC1_PARENT	mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC);
include/asm-ppc/ibm44x.h +106 -14

189 lines not on this page · raw message

include/asm-ppc/ibm4xx.h +4 -0
index 92fd02d..6945d9b 100644
@@ -109,6 +109,10 @@ void ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5,
 #include <platforms/4xx/ocotea.h>
 #endif
 
+#if defined(CONFIG_SEQUOIA) || defined(CONFIG_RAINIER)
+#include <platforms/4xx/sequoia.h>
+#endif
+
 #if defined(CONFIG_TAISHAN)
 #include <platforms/4xx/taishan.h>
 #endif
include/asm-ppc/ibm_ocp.h +7 -0
index ddce616..66d376b 100644
@@ -28,6 +28,7 @@
 struct ocp_sys_info_data {
 	int	opb_bus_freq;	/* OPB Bus Frequency (Hz) */
 	int	ebc_bus_freq;	/* EBC Bus Frequency (Hz) */
+	int	plb_bus_freq;	/* PLB Bus Frequency (Hz) */
 };
 
 extern struct ocp_sys_info_data ocp_sys_info;

@@ -67,6 +68,8 @@ struct ocp_func_emac_data {
 	u8	mac_addr[6];	/* EMAC mac address */
 	u32	phy_map;	/* EMAC phy map */
 	u32	phy_feat_exc;	/* Excluded PHY features */
+	int 	txcoal_irq;	/* Interrupt coalescence TX IRQ  */
+	int 	rxcoal_irq;	/* Interrupt coalescence RX IRQ */
 };
 
 /* Sysfs support */

@@ -84,6 +87,8 @@ OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, tah_idx)	\
 OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, phy_mode)	\
 OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_map)	\
 OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_feat_exc)\
+OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, txcoal_irq)	\
+OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rxcoal_irq)	\
 									\
 void ocp_show_emac_data(struct device *dev)				\
 {									\

@@ -100,6 +105,8 @@ void ocp_show_emac_data(struct device *dev)				\
 	device_create_file(dev, &dev_attr_emac_phy_mode);		\
 	device_create_file(dev, &dev_attr_emac_phy_map);		\
 	device_create_file(dev, &dev_attr_emac_phy_feat_exc);		\
+	device_create_file(dev, &dev_attr_emac_txcoal_irq);		\
+	device_create_file(dev, &dev_attr_emac_rxcoal_irq);		\
 }
 
 /*