One more patch for the sequoia --- This time to get a fater EBC on newer 666.66 MHz processors

[PATCH] Because the Sequoia board does not boot with an EBC faster than 66MHz,
the clock divider are changed after the initial boot process.

This allows for maximum clocking speeds to be achieved on newer boards. Sequoia boards with 666.66 MHz processors require that the EBC divider be set
to 3 in order to start the initial boot process at a slower EBC speed. After
the initial boot process, the divider can be set back to 2, which will cause the
boards to run at 83.333MHz. This is backward compatible with boards with

533.33 MHz processors, as these boards will already be set with an EBC divider
of 2.

---
Stefan: how's my formating this time?

 board/amcc/sequoia/sequoia.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

index 930fa71..80f2498
@@ -132,6 +132,12 @@ int board_early_init_f(void)
   (0x80000000 >> (28 + CFG_NAND_CS));
  mtsdr(SDR0_CUST0, sdr0_cust0);
 
+ /* Update EBC speed after booting from i2c bootstrap settings *
+  * on newer boards with 33.333 MHZ Clocks                     */
+ if (in8(CFG_BCSR_BASE + 3) & 0x80) {
+  mtdcr(0xc, 0xe0);
+  mtdcr(0xd, 0x02000000);
+ }
  return 0;
 }
 

1.4.1

Dear Jeff,

Ba, as indentation has to be done by TAB characters (multiple of 8 columns):

DENX Software Engineering GmbH,    CEO: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
It is surely a great calamity for  a  human  being  to  have  no  ob-
sessions.                                                - Robert Bly

Hi Jeff,

Additional to Wolfgang's comments:

- Your mailer has wrapped the commit text above. Please you shorter lines next time
- The subject line is still way too long. Please try to find a short one line subject for the patch like:
"[PATCH] ppc4xx: Fix Sequoia EBC configuration for new board revision"

Thanks.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH, HRB 165235 Munich, CEO: Wolfgang Denk
Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
=====================================================================

I've tried again. (attched this time so that OUTLOOK does not mess up the formating.)

Explanation of attached patch:

Because the Sequoia board does not boot with an EBC faster than 66MHz, the clock divider are changed after the initial boot process.

This allows for maximum clocking speeds to be achieved on newer boards. Sequoia boards with 666.66 MHz processors require that the EBC divider be set to 3 in order to start the initial boot process at a slower EBC speed. After the initial boot process, the divider can be set back to 2,

which will cause the boards to run at 83.333MHz. This is backward compatible with boards with 533.33 MHz processors, as these boards will already be set with an EBC divider of 2.

-Jeffrey Mann
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Hi Jeff,

I made small cosmetic changes. Please give the attached version a try and let me know if it still works for you. Thanks.

index 930fa71..8704014 100644
@@ -132,6 +132,12 @@ int board_early_init_f(void)
 		(0x80000000 >> (28 + CFG_NAND_CS));
 	mtsdr(SDR0_CUST0, sdr0_cust0);
 
+	/* Update EBC speed after booting from i2c bootstrap settings
+	 * on newer boards with 33.333 MHZ Clocks
+	 */
+	if (in8(CFG_BCSR_BASE + 3) & 0x80)
+		mtcpr(0xe0, 0x02000000);
+
 	return 0;
 }
 

@@ -363,8 +369,8 @@ int checkboard(void)
 	printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
 #endif
 
-	rev = *(u8 *)(CFG_BCSR_BASE + 0);
-	val = *(u8 *)(CFG_BCSR_BASE + 5) & 0x01;
+	rev = in8(CFG_BCSR_BASE + 0);
+	val = in8(CFG_BCSR_BASE + 5) & 0x01;
 	printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
 
 	if (s != NULL) {

index bc1d7aa..07f75de 100644
@@ -1425,9 +1425,6 @@
 /*----------------------------------------------------------------------------+
 | Clock / Power-on-reset DCR's.
 +----------------------------------------------------------------------------*/
-#define CPR0_CFGADDR			0x00C
-#define CPR0_CFGDATA			0x00D
-
 #define CPR0_CLKUPD			0x20
 #define CPR0_CLKUPD_BSY_MASK		0x80000000
 #define CPR0_CLKUPD_BSY_COMPLETED	0x00000000

@@ -3314,6 +3311,23 @@
 #define mtsdr(reg, data)	do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0)
 #define mfsdr(reg, data)	do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0)
 
+/*
+ * All 44x except 440GP have CPR registers (indirect DCR)
+ */
+#if !defined(CONFIG_440GP)
+#define CPR0_CFGADDR		0x00C
+#define CPR0_CFGDATA		0x00D
+
+#define mtcpr(reg, data)	do { \
+		mtdcr(CPR0_CFGADDR, reg); \
+		mtdcr(CPR0_CFGDATA, data); \
+	} while (0)
+
+#define mfcpr(reg, data)	do { \
+		mtdcr(CPR0_CFGADDR, reg); \
+		data = mfdcr(CPR0_CFGDATA); \
+	} while (0)
+#endif
 
 #ifndef __ASSEMBLY__