problem with converting from at91_spi to atmel_spi (AT91RM9200)

Ivan Kuten

author

2007-05-23 11:34 UTC #0 lore raw

Hello,

I'm trying to convert from legacy at91_spi to newer atmel_spi driver in my board. Linux kernel 2.6.22rc2 + corresponding patch from maxim.org.za/at91_26.html

board specific spi info :

static struct spi_board_info chub_spi_devices[] = {
{ /* DataFlash chip */
.modalias = "mtd_dataflash",
.chip_select = 0,
.max_speed_hz = 15 * 1000 * 1000,
},
};

snip from .config:

CONFIG_MTD_DATAFLASH=y

#
# SPI support
#
CONFIG_SPI=y
CONFIG_SPI_DEBUG=y
CONFIG_SPI_MASTER=y

#
# SPI Master Controller Drivers
#
CONFIG_SPI_ATMEL=y
# CONFIG_SPI_BITBANG is not set
CONFIG_SPI_AT91_MANUAL_CS=y
#
# SPI Protocol Masters
#
# CONFIG_SPI_AT25 is not set
# CONFIG_SPI_SPIDEV is not set

While boot, the board stumbles on SPI initialization:

Uncompressing Linux....................................................................... done, booting the kernel. Linux version 2.6.22-rc1 (vano@newbox) (gcc version 3.4.2) #12 Wed May 23 14:05:30 EEST 2007
CPU: ARM920T [41129200] revision 0 (ARMv4T), cr=c0007177
Machine: Promwad Chub
---snip----
eth0: Link now 100-FullDuplex
eth0: AT91 ethernet at 0xfefbc000 int=24 100-FullDuplex (00:12:34:56:78:9a)
eth0: National Semiconductor DP83848 PHY
NAND device: Manufacturer ID: 0xec, Chip ID: 0x76 (Samsung NAND 64MiB 3,3V 8-bit)
Scanning device for bad blocks
Creating 1 MTD partitions on "NAND 64MiB 3,3V 8-bit":
0x00000000-0x04000000 : "NAND Partition 1"
atmel_spi atmel_spi.0: Atmel SPI Controller at 0xfffe0000 (irq 13)

Not booting further. Timer led is still blinking. Is atmel_spi usable?
I have working setup on 2.6.20 + corresponding patch from maxim.org.za/at91_26.html + legacy "at91_dataflash" + legacy "at91_spi"

Best regards, Ivan

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David Brownell

2007-05-23 16:06 UTC #1 lore raw

Quoted 5 lines · Ivan Kuten

Hello,
I'm trying to convert from legacy at91_spi to newer atmel_spi driver in my board. Linux kernel 2.6.22rc2 + corresponding patch from maxim.org.za/at91_26.html

This is AT91rm9200, yes?

Quoted 6 lines

board specific spi info :
static struct spi_board_info chub_spi_devices[] = {
{ /* DataFlash chip */
.modalias = "mtd_dataflash",
.chip_select = 0,

Chipselect zero ... I've had one report that this driver has some issues on that chipselect. There seem to be two errata in conflict here:

- One saying that when the controller manages chipselects, it does so incorrectly ... releasing it before it's told to do so, which prematurely terminates transactions. ("NPCSx rises if no data is to be transmitted")

- Another saying that if it does *not* manage chipselects, then broken mode fault detect logic kicks in; this could be what you're seeing. ("Mode Fault does not allow more than one master on Chip Select 0")

I've CC'd the relevant folk from Atmel. Seems that maybe rm9200 needs to have a special case whereby chipselect zero is managed by the hardware despite the first erratum. And maybe that because of that erratum, the DMA chaining needs to be made to work... else root-on-dataflash won't behave. (Or some other workaround.)

- Dave

Quoted 43 lines

                .max_speed_hz   = 15 * 1000 * 1000,
        },
};
snip from .config:
CONFIG_MTD_DATAFLASH=y
#
# SPI support
#
CONFIG_SPI=y
CONFIG_SPI_DEBUG=y
CONFIG_SPI_MASTER=y
#
# SPI Master Controller Drivers
#
CONFIG_SPI_ATMEL=y
# CONFIG_SPI_BITBANG is not set
CONFIG_SPI_AT91_MANUAL_CS=y
#
# SPI Protocol Masters
#
# CONFIG_SPI_AT25 is not set
# CONFIG_SPI_SPIDEV is not set
While boot, the board stumbles on SPI initialization:
Uncompressing Linux....................................................................... done, booting the kernel. Linux version 2.6.22-rc1 (vano@newbox) (gcc version 3.4.2) #12 Wed May 23 14:05:30 EEST 2007
CPU: ARM920T [41129200] revision 0 (ARMv4T), cr=c0007177
Machine: Promwad Chub
---snip----
eth0: Link now 100-FullDuplex
eth0: AT91 ethernet at 0xfefbc000 int=24 100-FullDuplex (00:12:34:56:78:9a)
eth0: National Semiconductor DP83848 PHY
NAND device: Manufacturer ID: 0xec, Chip ID: 0x76 (Samsung NAND 64MiB 3,3V 8-bit)
Scanning device for bad blocks
Creating 1 MTD partitions on "NAND 64MiB 3,3V 8-bit":
0x00000000-0x04000000 : "NAND Partition 1"
atmel_spi atmel_spi.0: Atmel SPI Controller at 0xfffe0000 (irq 13)

Quoted 8 lines

Not booting further. Timer led is still blinking. Is atmel_spi usable? I have working setup on 2.6.20 + corresponding patch from maxim.org.za/at91_26.html + legacy "at91_dataflash" + legacy "at91_spi"
Best regards, Ivan

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Ivan Kuten

author

2007-05-23 16:29 UTC #3 lore raw

Hi David,

Quoted 3 lines

This is AT91rm9200, yes?

Correct, it's AT91RM9200.

While trying to catch your thought regarding chip selects & errata, I just note that in mach-at91/*.c there are some boards which use dataflash and "mtd_dataflash" driver with SPI chip select 0, for example board-ek.c, board-carmeva.c, board-dk.c. I can't believe all of them has non-working dataflash (certainly at they was tested).

Best regards, Ivan

Quoted 30 lines · On Wed, 23 May 2007 09:06:12 -0700 David Brownell wrote:

Quoted 5 lines · Ivan Kuten
Hello,
I'm trying to convert from legacy at91_spi to newer atmel_spi driver in my board. Linux kernel 2.6.22rc2 + corresponding patch from maxim.org.za/at91_26.html
This is AT91rm9200, yes?
Quoted 6 lines
board specific spi info :
static struct spi_board_info chub_spi_devices[] = {
{ /* DataFlash chip */
.modalias = "mtd_dataflash",
.chip_select = 0,
Chipselect zero ... I've had one report that this driver has some issues on that chipselect. There seem to be two errata in conflict here:
- One saying that when the controller manages chipselects, it does so incorrectly ... releasing it before it's told to do so, which prematurely terminates transactions. ("NPCSx rises if no data is to be transmitted")
- Another saying that if it does *not* manage chipselects, then broken mode fault detect logic kicks in; this could be what you're seeing. ("Mode Fault does not allow more than one master on Chip Select 0")

Quoted 60 lines

I've CC'd the relevant folk from Atmel. Seems that maybe rm9200 needs to have a special case whereby chipselect zero is managed by the hardware despite the first erratum. And maybe that because of that erratum, the DMA chaining needs to be made to work... else root-on-dataflash won't behave. (Or some other workaround.)
- Dave
Quoted 51 lines
                .max_speed_hz   = 15 * 1000 * 1000,
        },
};
snip from .config:
CONFIG_MTD_DATAFLASH=y
#
# SPI support
#
CONFIG_SPI=y
CONFIG_SPI_DEBUG=y
CONFIG_SPI_MASTER=y
#
# SPI Master Controller Drivers
#
CONFIG_SPI_ATMEL=y
# CONFIG_SPI_BITBANG is not set
CONFIG_SPI_AT91_MANUAL_CS=y
#
# SPI Protocol Masters
#
# CONFIG_SPI_AT25 is not set
# CONFIG_SPI_SPIDEV is not set
While boot, the board stumbles on SPI initialization:
Uncompressing Linux....................................................................... done, booting the kernel. Linux version 2.6.22-rc1 (vano@newbox) (gcc version 3.4.2) #12 Wed May 23 14:05:30 EEST 2007
CPU: ARM920T [41129200] revision 0 (ARMv4T), cr=c0007177
Machine: Promwad Chub
---snip----
eth0: Link now 100-FullDuplex
eth0: AT91 ethernet at 0xfefbc000 int=24 100-FullDuplex (00:12:34:56:78:9a)
eth0: National Semiconductor DP83848 PHY
NAND device: Manufacturer ID: 0xec, Chip ID: 0x76 (Samsung NAND 64MiB 3,3V 8-bit)
Scanning device for bad blocks
Creating 1 MTD partitions on "NAND 64MiB 3,3V 8-bit":
0x00000000-0x04000000 : "NAND Partition 1"
atmel_spi atmel_spi.0: Atmel SPI Controller at 0xfffe0000 (irq 13)
Not booting further. Timer led is still blinking. Is atmel_spi usable? I have working setup on 2.6.20 + corresponding patch from maxim.org.za/at91_26.html + legacy "at91_dataflash" + legacy "at91_spi"
Best regards, Ivan

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Haavard Skinnemoen

2007-05-24 11:36 UTC #4 lore raw

In reply to a message not in the archive

Quoted 16 lines · On Wed, 23 May 2007 09:06:12 -0700 David Brownell <[email protected]> wrote:

Quoted 6 lines · Ivan Kuten
board specific spi info :
static struct spi_board_info chub_spi_devices[] = {
{ /* DataFlash chip */
.modalias = "mtd_dataflash",
.chip_select = 0,
Chipselect zero ... I've had one report that this driver has some issues on that chipselect. There seem to be two errata in conflict here:
- One saying that when the controller manages chipselects, it does so incorrectly ... releasing it before it's told to do so, which prematurely terminates transactions. ("NPCSx rises if no data is to be transmitted")

Quoted 4 lines

- Another saying that if it does *not* manage chipselects, then broken mode fault detect logic kicks in; this could be what you're seeing. ("Mode Fault does not allow more than one master on Chip Select 0")

Neither of these should cause any problems for the atmel_spi driver since it manages chip selects using gpio and sets the MODFDIS bit in MR to disable mode fault detection (I actually ran into both erratas myself while developing the driver.)

And I did actually test the driver on STK1000 with an add-on board connecting a dataflash chip to cs0 on the second SPI controller. But this was on the AT32AP7000 which uses a newer version of the SPI controller...

Quoted 5 lines

I've CC'd the relevant folk from Atmel. Seems that maybe rm9200 needs to have a special case whereby chipselect zero is managed by the hardware despite the first erratum. And maybe that because of that erratum, the DMA chaining needs to be made to work... else root-on-dataflash won't behave. (Or some other workaround.)

Hmm...I don't think I understand why DMA chaining will help in this case. Could you explain a bit more?

Quoted 9 lines

Quoted 9 lines
eth0: Link now 100-FullDuplex
eth0: AT91 ethernet at 0xfefbc000 int=24 100-FullDuplex (00:12:34:56:78:9a)
eth0: National Semiconductor DP83848 PHY
NAND device: Manufacturer ID: 0xec, Chip ID: 0x76 (Samsung NAND 64MiB 3,3V 8-bit) Scanning device for bad blocks
Creating 1 MTD partitions on "NAND 64MiB 3,3V 8-bit":
0x00000000-0x04000000 : "NAND Partition 1"
atmel_spi atmel_spi.0: Atmel SPI Controller at 0xfffe0000 (irq 13)

Quoted 3 lines

Quoted 3 lines
Not booting further. Timer led is still blinking. Is atmel_spi usable? I have working setup on 2.6.20 + corresponding patch from maxim.org.za/at91_26.html + legacy "at91_dataflash" + legacy "at91_spi"

Is there any way you can get a dump of what the CPU is doing? Magic SysRq, NMI, etc?

Håvard

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David Brownell

2007-05-24 16:31 UTC #6 lore raw

Quoted 6 lines · Haavard Skinnemoen

Quoted 4 lines · On Wed, 23 May 2007 09:06:12 -0700 David Brownell…
Quoted 2 lines · Ivan Kuten
.chip_select = 0,

Quoted 8 lines

Quoted 3 lines
Chipselect zero ... I've had one report that this driver has some issues on that chipselect. There seem to be two errata in conflict here:
...
Neither of these should cause any problems for the atmel_spi driver since it manages chip selects using gpio and sets the MODFDIS bit in MR to disable mode fault detection (I actually ran into both erratas myself while developing the driver.)

Yet, I got the report (at91rm9200 specific). Bill? (I remember MODFDIS acting oddly, non-rm9200, but forget the details.) And in any case there seem to be other folk reporting rm9200 + dataflash issues ... while mtd_dataflash doesn't seem to be at fault. So maybe that combination of errata isn't the issue, but something else is making the problem.

Quoted 8 lines

Quoted 5 lines
I've CC'd the relevant folk from Atmel. Seems that maybe rm9200 needs to have a special case whereby chipselect zero is managed by the hardware despite the first erratum. And maybe that because of that erratum, the DMA chaining needs to be made to work... else root-on-dataflash won't behave. (Or some other workaround.)
Hmm...I don't think I understand why DMA chaining will help in this case. Could you explain a bit more?

It *might* help -- by keeping the transfer buffer busy enough that the "auto-deselect" erratum needn't kick in with some basic request and response protocol operations.

- Dave

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Bill Gatliff

2007-05-24 17:20 UTC #8 lore raw

David:

Quoted 7 lines · David Brownell

Yet, I got the report (at91rm9200 specific). Bill? (I remember MODFDIS acting oddly, non-rm9200, but forget the details.) And in any case there seem to be other folk reporting rm9200 + dataflash issues ... while mtd_dataflash doesn't seem to be at fault. So maybe that combination of errata isn't the issue, but something else is making the problem.

Good recall! :)

Rev. F of the AT91RM9200 manual says, in 41.9.4:

"If Mode fault is disabled, Chip Select 0 cannot be driven by a component other than the SPI otherwise the transfer does not occur".

... but if you enable mode faulting, something else breaks IIRC.

IOW, CS0 for the 9200 doesn't work if the SPI controls it. And SPI doesn't work for CS0 if the SPI controller _doesn't_ control it, either. So I've just quit using CS0. :(

At least, that's where I left it with 2.6.20 during my investigations. Haven't come back to this topic since then.

b.g.

Signature · 2 lines

Bill Gatliff
bgat-uPd5UNENI//[email protected]

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Ivan Kuten

author

2007-05-24 18:24 UTC #10 lore raw

Quoted 11 lines · On Thu, 24 May 2007 12:20:22 -0500 Bill Gatliff wrote:

Rev. F of the AT91RM9200 manual says, in 41.9.4:
"If Mode fault is disabled, Chip Select 0 cannot be driven by a component other than the SPI otherwise the transfer does not occur".
... but if you enable mode faulting, something else breaks IIRC.
IOW, CS0 for the 9200 doesn't work if the SPI controls it. And SPI doesn't work for CS0 if the SPI controller _doesn't_ control it, either. So I've just quit using CS0. :(

So I assume AT91RM9200 boards such as:

static struct spi_board_info ek_spi_devices[] = {
{ /* DataFlash chip */
.modalias = "mtd_dataflash",
.chip_select = 0,
.max_speed_hz = 15 * 1000 * 1000,
},

static struct spi_board_info carmeva_spi_devices[] = {
        { /* DataFlash chip */
                .modalias = "mtd_dataflash",
                .chip_select  = 0,
                .max_speed_hz = 10 * 1000 * 1000,
        },

static struct spi_board_info dk_spi_devices[] = {
{ /* DataFlash chip */
.modalias = "mtd_dataflash",
.chip_select = 0,
.max_speed_hz = 15 * 1000 * 1000,
},

are broken cause all of them have chip_select = 0 ?

BR, Ivan

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Bill Gatliff

2007-05-24 18:43 UTC #11 lore raw

Ivan:

Quoted 16 lines · Ivan Kuten

So I assume AT91RM9200 boards such as:
static struct spi_board_info ek_spi_devices[] = {
{ /* DataFlash chip */
.modalias = "mtd_dataflash",
.chip_select = 0,
.max_speed_hz = 15 * 1000 * 1000,
},
static struct spi_board_info carmeva_spi_devices[] = {
        { /* DataFlash chip */
                .modalias = "mtd_dataflash",
                .chip_select  = 0,
                .max_speed_hz = 10 * 1000 * 1000,
        },

Quoted 9 lines

static struct spi_board_info dk_spi_devices[] = {
{ /* DataFlash chip */
.modalias = "mtd_dataflash",
.chip_select = 0,
.max_speed_hz = 15 * 1000 * 1000,
},
are broken cause all of them have chip_select = 0 ?

Dunno. The problem might be confined to a particular stepping of the chip. It could also be that I'm wrong. :)

b.g.

Signature · 9 lines

Bill Gatliff
bgat-uPd5UNENI//[email protected]


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Andrew Victor

2007-05-25 07:07 UTC #12 lore raw

In reply to Ivan Kuten

hi,

Quoted 8 lines

static struct spi_board_info dk_spi_devices[] = {
{ /* DataFlash chip */
.modalias = "mtd_dataflash",
.chip_select = 0,
.max_speed_hz = 15 * 1000 * 1000,
},
are broken cause all of them have chip_select = 0 ?

I doubt it.

The DK board definitely works.
All SAN People's RM9200-based products have DataFlash on CS0 - boot from CS0, mount root filesystem (cramfs) on CS0, writable JFFS2 partition on CS0.

That's with legacy SPI and at91_dataflash.c. (ie, CS0 under SPI control).

Regards,
Andrew Victor

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Ivan Kuten

author

2007-05-25 14:19 UTC #14 lore raw

Quoted 13 lines · On 25 May 2007 09:07:24 +0200 Andrew Victor wrote:

hi,
Quoted 8 lines
static struct spi_board_info dk_spi_devices[] = {
{ /* DataFlash chip */
.modalias = "mtd_dataflash",
.chip_select = 0,
.max_speed_hz = 15 * 1000 * 1000,
},
are broken cause all of them have chip_select = 0 ?
I doubt it.

Quoted 8 lines

The DK board definitely works.
All SAN People's RM9200-based products have DataFlash on CS0 - boot from CS0, mount root filesystem (cramfs) on CS0, writable JFFS2 partition on CS0.
That's with legacy SPI and at91_dataflash.c. (ie, CS0 under SPI control).

In such a case it should have

static struct spi_board_info dk_spi_devices[] = {
{ /* DataFlash chip */
// .modalias = "mtd_dataflash",

                 .modalias       = "at91_dataflash",
                 .chip_select    = 0,
                 .max_speed_hz   = 15 * 1000 * 1000,
         },

Cause from my understanding "mtd_dataflash" triggers usage of new SPI framework (driver/spi/atmel_spi.c).

What I currently have:
at91_dataflash.c + 2.6.20+maxim + legacy SPI - working at91_dataflash.c + 2.6.22rc1+maxim + legacy SPI - not working mtd_dataflash.c + 2.6.20+maxim + atmel_spi.c - not working mtd_dataflash.c + 2.6.22rc1+maxim + atmel_spi.c - not working

Now I'm trying understand what was changed between 2.6.20+maxim and 2.6.22rc1+maxim

Best regards, Ivan

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Andrew Victor

2007-05-25 14:41 UTC #15 lore raw

hi Ivan,

Quoted 9 lines

In such a case it should have
static struct spi_board_info dk_spi_devices[] = {
{ /* DataFlash chip */
// .modalias = "mtd_dataflash",
                 .modalias       = "at91_dataflash",
                 .chip_select    = 0,
                 .max_speed_hz   = 15 * 1000 * 1000,
         },

Makes no difference for the legacy SPI drivers. If they are used, the only field in this structure which is checked is "chip_select" so at91_add_device_spi() can configure the pin (GPIO vs A_periph).

What is important is what SPI_DEVNAME is set to in at91rm9200_devices.c.

#if defined(CONFIG_AT91_SPI) || defined(CONFIG_AT91_SPI_MODULE) /* legacy SPI driver */
#define SPI_DEVNAME "at91_spi"

#elif defined(CONFIG_SPI_AT91) || defined(CONFIG_SPI_AT91_MODULE) /* SPI bitbanging driver */
#define SPI_DEVNAME "at91_spi"

#elif defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) /* new SPI driver */
#define SPI_DEVNAME "atmel_spi"

And that depends on what SPI driver(s) you have enabled in the configuration.

Changes since 2.6.19.....

at91_dataflash.c:
- device->flags = MTD_CAP_NORFLASH;
+ device->flags = MTD_WRITEABLE;

at91_spi.c:
asm/arch/at91rm9200_pdc.h replaced with linux/atmel_pdc.h AT91_PDC_* definitions replaced with ATMEL_PDC_*

Regards,
Andrew Victor

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David Brownell

2007-05-25 16:51 UTC #16 lore raw

In reply to Ivan Kuten

Quoted 12 lines · Ivan Kuten

Quoted 9 lines · On 25 May 2007 09:07:24 +0200 Andrew Victor wrote:
hi,
Quoted 4 lines
static struct spi_board_info dk_spi_devices[] = {
        ...
are broken cause all of them have chip_select = 0 ?
I doubt it.

Quoted 7 lines

Quoted 7 lines
The DK board definitely works.
All SAN People's RM9200-based products have DataFlash on CS0 - boot from CS0, mount root filesystem (cramfs) on CS0, writable JFFS2 partition on CS0.
That's with legacy SPI and at91_dataflash.c. (ie, CS0 under SPI control).

It'd be good if someone with some rm9200 board that can boot from DataFlash tried a version of the atmel_spi config that leaves CS0 under control of the SPI controller ... updating the setup code would suffice, ISTR.

Because we know that both atmel_spi and mtd_datflash behave on other hardware, even for CS0. And ISTR hearing they work OK on rm9200, for other chipselects...

- Dave

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Bill Gatliff

2007-05-25 16:54 UTC #18 lore raw

David:

Quoted 5 lines · David Brownell

It'd be good if someone with some rm9200 board that can boot from DataFlash tried a version of the atmel_spi config that leaves CS0 under control of the SPI controller ... updating the setup code would suffice, ISTR.

Alas, I have no such board. Sorry!

b.g.

Signature · 9 lines

Bill Gatliff
bgat-uPd5UNENI//[email protected]


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Ivan Kuten

author

2007-05-25 15:02 UTC #19 lore raw

In reply to a message not in the archive

Quoted 5 lines · On Thu, 24 May 2007 13:36:46 +0200 Haavard Skinnemoen wrote:

Is there any way you can get a dump of what the CPU is doing? Magic SysRq, NMI, etc?
Håvard

Unfortunately I could not get SysRq working on Ateml dbgu. I installed GPIO IRQ handler

static irqreturn_t chubpower_irq_handler(int irq, void *context)

{
        printk(KERN_EMERG "Power!\n");
        dump_stack();
        return IRQ_HANDLED;
}

and triggered it when the system stumbled on Dataflash init, also I added some printks:

eth0: Link now 100-FullDuplex
eth0: AT91 ethernet at 0xfefbc000 int=24 100-FullDuplex (00:12:34:56:78:9a)
eth0: National Semiconductor DP83848 PHY
spi_register_driver : line 163
enter atmel_spi_probe : line 546
atmel_spi_probe : line 603
atmel_spi atmel_spi.0: Atmel SPI Controller at 0xfffe0000 (irq 13) spi_register_master : line 428
scan_boardinfo : line 318
spi_new_device : line 213
enter atmel_spi_setup : line 390
leave atmel_spi_setup : line 462
spi_drv_probe : line 136
dataflash_probe : line 536
dataflash_status : line 114
enter spi_w8r8 : line 617
enter spi_write_then_read : line 596
before spi_sync spi_write_then_read : line 629
enter atmel_spi_transfer : line 474
enter atmel_spi_dma_map_xfer : line 201
leave atmel_spi_dma_map_xfer : line 212
enter atmel_spi_dma_map_xfer : line 201
leave atmel_spi_dma_map_xfer : line 212
enter atmel_spi_next_message : line 182
cs_activate : line 77
enter atmel_spi_next_xfer : line 106
leave atmel_spi_next_xfer : line 173
leave atmel_spi_next_message : line 195
leave atmel_spi_transfer : line 524
Power!
[<c0023e60>] (dump_stack+0x0/0x14) from [<c0029440>] (chubpower_irq_handler+0x18/0x24) [<c0029428>] (chubpower_irq_handler+0x0/0x24) from [<c0054980>] (handle_IRQ_event+0x44/0x80) [<c005493c>] (handle_IRQ_event+0x0/0x80) from [<c0055c18>] (handle_simple_irq+0x80/0xb4)
r7:00000003 r6:00000001 r5:0000005c r4:c01e4284
[<c0055b98>] (handle_simple_irq+0x0/0xb4) from [<c0029298>] (gpio_irq_handler+0xa0/0xcc)
r5:c01e4284 r4:0000005c
[<c00291f8>] (gpio_irq_handler+0x0/0xcc) from [<c001f048>] (asm_do_IRQ+0x48/0x70) [<c001f000>] (asm_do_IRQ+0x0/0x70) from [<c001fac4>] (__irq_svc+0x24/0x60)

Exception stack(0xc01ddf50 to 0xc01ddf98)

df40: 00000000 fefff830 00000000 60000013
df60: c01dc000 c0020908 c01dff78 c02082ec 2001c184 41129200 2001c150 c01ddfa4
df80: c01ddfa8 c01ddf98 c0020948 c0020954 60000013 ffffffff
r7:c02082ec r6:00000003 r5:fefff000 r4:ffffffff
[<c0020908>] (default_idle+0x0/0x54) from [<c00209b4>] (cpu_idle+0x58/0x7c) [<c002095c>] (cpu_idle+0x0/0x7c) from [<c001f2bc>] (__exception_text_end+0x48/0x58)
r6:c001df28 r5:c01efe48 r4:c01f8ae4
[<c001f274>] (__exception_text_end+0x0/0x58) from [<c0008ab8>] (start_kernel+0x27c/0x2e4) [<c000883c>] (start_kernel+0x0/0x2e4) from [<20008030>] (0x20008030)
r6:c01dfc54 r5:c01f0304 r4:c0007175

Seems it was in the idle state.

BR,
Ivan

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Haavard Skinnemoen

2007-05-25 15:55 UTC #20 lore raw

Quoted 5 lines · On Fri, 25 May 2007 18:02:36 +0300 Ivan Kuten <[email protected]> wrote:

On Thu, 24 May 2007 13:36:46 +0200
Haavard Skinnemoen wrote:
Unfortunately I could not get SysRq working on Ateml dbgu. I installed GPIO IRQ handler

Right. I remember posting a patch to fix it, but rmk found some issues with it and I never really got around to fix the issues he complained about...

Quoted 10 lines

static irqreturn_t chubpower_irq_handler(int irq, void *context)
{
        printk(KERN_EMERG "Power!\n");
        dump_stack();
        return IRQ_HANDLED;
}
and triggered it when the system stumbled on Dataflash init, also I added some printks:
Seems it was in the idle state.

Hmm...not too surprising really. Could you add a call to show_state() as well? I suspect it will just show init waiting for completion in spi_sync() though.

What might be more interesting is a dump of the contents of the SPI controller registers, i.e. something like this:

	void *p;
	int i;

	p = ioremap(0xfffe0000);
	for (i = 0; i < 0x100; i += 16)
		printk("%04x: %08x %08x %08x %08x\n", i,
			readl(p + i), readl(p + i + 4),
			readl(p + i + 8), readl(p + i + 12));
	iounmap(p);

Could you add that?

Håvard

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Ivan Kuten

author

2007-05-26 14:02 UTC #22 lore raw

Quoted 5 lines · On Fri, 25 May 2007 17:55:02 +0200 Haavard Skinnemoen wrote:

Hmm...not too surprising really. Could you add a call to show_state() as well? I suspect it will just show init waiting for completion in spi_sync() though.

Haavard, log with show_state() is attached, seems you are right it's waiting for completion.

[<c017f040>] (schedule+0x0/0x750) from [<c017f83c>] (wait_for_completion+0xac/0x110) [<c017f790>] (wait_for_completion+0x0/0x110) from [<c0120018>] (spi_sync+0x54/0x68)
r6:00000000 r5:c0405c78 r4:c0405c00
[<c011ffc4>] (spi_sync+0x0/0x68) from [<c0120170>] (spi_write_then_read+0x144/0x204)
r7:c01eb978 r6:c0405c78 r5:c06aa6e0 r4:00000001
[<c012002c>] (spi_write_then_read+0x0/0x204) from [<c011f664>] (dataflash_probe+0x6c/0x244) [<c011f5f8>] (dataflash_probe+0x0/0x244) from [<c011f99c>] (spi_drv_probe+0x3c/0x48)
r6:c01eb634 r5:00000000 r4:c03ea200
[<c011f960>] (spi_drv_probe+0x0/0x48) from [<c0104e7c>] (driver_probe_device+0xe8/0x18c)
r4:c03ea200
[<c0104d94>] (driver_probe_device+0x0/0x18c) from [<c0104f30>] (__device_attach+0x10/0x14)

Quoted 13 lines

What might be more interesting is a dump of the contents of the SPI controller registers, i.e. something like this:
	void *p;
	int i;

	p = ioremap(0xfffe0000);
	for (i = 0; i < 0x100; i += 16)
		printk("%04x: %08x %08x %08x %08x\n", i,
			readl(p + i), readl(p + i + 4),
			readl(p + i + 8), readl(p + i + 12));
	iounmap(p);

Here is dump of SPI regs:

Power!
0000: 00000000 000e0011 00000000 00000000
0010: 000100a0 00000000 00000000 00000018
0020: 00000000 00000000 00000000 00000000
0030: 0a0a0202 00000000 00000000 00000000
0040: 00000000 00000000 00000000 00000000
0050: 00000000 00000000 00000000 00000000
0060: 00000000 00000000 00000000 00000000
0070: 00000000 00000000 00000000 00000000
0080: 00000000 00000000 00000000 00000000
0090: 00000000 00000000 00000000 00000000
00a0: 00000000 00000000 00000000 00000000
00b0: 00000000 00000000 00000000 00000000
00c0: 00000000 00000000 00000000 00000000
00d0: 00000000 00000000 00000000 00000000
00e0: 00000000 00000000 00000000 00000000
00f0: 00000000 00000000 00000000 00000000

P.S. I placed ioremap outside irq handler, otherwise it complains kernel BUG at mm/vmalloc.c:171!

Unable to handle kernel NULL pointer dereference at virtual address 00000000

pgd = c0004000
[00000000] *pgd=00000000

BR,
Ivan

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Haavard Skinnemoen

2007-05-27 12:45 UTC #23 lore raw

Quoted 5 lines · On Sat, 26 May 2007 17:02:25 +0300 Ivan Kuten <[email protected]> wrote:

Here is dump of SPI regs:
Power!
0000: 00000000 000e0011 00000000 00000000
0010: 000100a0 00000000 00000000 00000018

This is interesting...SR has SPIENS, TXBUFE and ENDTX bits set, nothing else. So the DMA transfer is complete on the TX side, but not for RX and the TX shifter still has data in it...

Ok, this _is_ actually the second errata -- it seems to trigger even if mode fault detection is turned off. I didn't know that, but the errata is actually quite clear: "If Mode fault is disabled, Chip Select 0 cannot be driven by a component other than the SPI otherwise the transfer does not occur."

Nicolas, do you know of any workaround for this? I suppose implementing DMA chaining would help, but it doesn't sound like an entirely watertight solution to me...

FWIW, the SAM9 and AP700x chips don't seem to have the same errata. They have a somewhat similar quirk which is that when mode fault checking is _enabled_, the SPI controller will refuse to start a transfer if CS0 is already low. This is why I disabled mode fault checking in the first place.

Quoted 5 lines

P.S. I placed ioremap outside irq handler, otherwise it complains kernel BUG at mm/vmalloc.c:171!
Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = c0004000
[00000000] *pgd=00000000

Right...ioremap can't be called from interrupt context. My bad.

Håvard

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Ivan Kuten

author

2007-05-24 15:27 UTC #24 lore raw

In reply to a message not in the archive

Quoted 9 lines · On Wed, 23 May 2007 09:06:12 -0700 David Brownell wrote:

Chipselect zero ... I've had one report that this driver has some issues on that chipselect. There seem to be two errata in conflict here:
- One saying that when the controller manages chipselects, it does so incorrectly ... releasing it before it's told to do so, which prematurely terminates transactions. ("NPCSx rises if no data is to be transmitted")

Quoted 5 lines

- Another saying that if it does *not* manage chipselects, then broken mode fault detect logic kicks in; this could be what you're seeing. ("Mode Fault does not allow more than one master on Chip Select 0")

David, as I understood new atmel_spi driver enables CONFIG_SPI_AT91_MANUAL_CS which in turn enables workaround for 1st errata item you mentioned

at91rm9200_devices.c
...
in at91_add_device_spi function:

#ifdef CONFIG_SPI_AT91_MANUAL_CS 
                at91_set_gpio_output(cs_pin, 1);
#else 
                at91_set_A_periph(cs_pin, 0);

#endif

Regarding second errata item - I have a single device (dataflash - 8MB) on SPI chip select 0, so I do not think this is an issue here.

Best regards, Ivan

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