Migrate esd 405EP boards to new NAND subsystem

PATCH New Matthias Fuchs 1 participant 1 message Jul 9, 2007

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Matthias Fuchs

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2007-07-09 09:00 UTC #0 lore raw

PATCH 2/3 Migrate esd 405EP boards to new NAND subsystem

Migrate esd 405EP boards to new NAND subsystem

-cleanup
-use correct io accessors (in/out_be32())

Signed-off-by Matthias Fuchs <[email protected]>

---
commit c170c46a2eb53855ede1b84c0a58c9029fa54279
tree c224017237869ba2d339e7babc55968260f83106
parent aa6e97ca6365f942967f2d062dc6b3998348eb2c
author Matthias Fuchs <[email protected]> Mon, 09 Jul 2007 09:57:17 +0200 committer Matthias Fuchs <[email protected]> Mon, 09 Jul 2007 09:57:17 +0200

 board/esd/ash405/Makefile |    4 ++-
 board/esd/ash405/ash405.c |   43 +++++++++-------------------------
 board/esd/cms700/Makefile |    5 +++-
 board/esd/cms700/cms700.c |   39 ++++++-------------------------
 board/esd/hh405/Makefile  |    5 +++-
 board/esd/hh405/hh405.c   |   22 +----------------
 board/esd/hub405/Makefile |    4 ++-
 board/esd/hub405/hub405.c |   34 ---------------------------
 board/esd/plu405/Makefile |    5 +++-
 board/esd/plu405/plu405.c |   56 +++++++-------------------------------------
 board/esd/voh405/Makefile |    4 ++-
 board/esd/voh405/voh405.c |   20 ----------------
 board/esd/wuh405/Makefile |    4 ++-
 board/esd/wuh405/wuh405.c |   33 --------------------------
 include/configs/ASH405.h  |   43 +++++++++-------------------------
 include/configs/CMS700.h  |   39 +++++++------------------------
 include/configs/HH405.h   |   39 +++++++------------------------
 include/configs/HUB405.h  |   39 +++++++------------------------
 include/configs/PLU405.h  |   57 +++++++--------------------------------------
 include/configs/VOH405.h  |   39 +++++++------------------------
 include/configs/WUH405.h  |   42 ++++++++-------------------------
 21 files changed, 120 insertions(+), 456 deletions(-)

board/esd/ash405/Makefile +3 -1

index 4d75868..308f752 100644
@@ -28,7 +28,9 @@ endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o flash.o ../common/misc.o
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/esd/ash405/ash405.c +11 ~~-32~~

76 lines not on this page · raw message

board/esd/cms700/Makefile +4 -1

index df48766..0d4ab2d 100644
@@ -33,7 +33,10 @@ CPLD    = ../common/xilinx_jtag/lenval.o
 	  ../common/xilinx_jtag/micro.o \
 	  ../common/xilinx_jtag/ports.o
 
-COBJS	= $(BOARD).o flash.o ../common/misc.o $(CPLD)
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	$(CPLD) \
+	../common/esd405ep_nand.o \
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/esd/cms700/cms700.c +8 ~~-31~~

index cb04710..81de5b2 100644
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2005
+ * (C) Copyright 2005-2007
  * Matthias Fuchs, esd gmbh germany, matthias.fuchs at esd-electronics.com
  *
  * See file CREDITS for list of people who contributed to this

@@ -23,6 +23,7 @@
 
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 #include <command.h>
 #include <malloc.h>

@@ -68,9 +69,9 @@ int board_early_init_f (void)
 	/*
 	 * Reset CPLD via GPIO12 (CS3) pin
 	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET);
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_PLD_RESET);
 	udelay(1000); /* wait 1ms */
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET);
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_PLD_RESET);
 	udelay(1000); /* wait 1ms */
 
 	return 0;

@@ -94,13 +95,7 @@ int misc_init_r (void)
  	/*
 	 * Setup and enable EEPROM write protection
 	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
-
-	/*
-	 * Set NAND-FLASH GPIO signals to default
-	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
 
 	return (0);
 }

@@ -153,11 +148,6 @@ long int initdram (int board_type)
 	mtdcr(memcfga, mem_mb0cf);
 	val = mfdcr(memcfgd);
 
-#if 0
-	printf("\nmb0cf=%x\n", val); /* test-only */
-	printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
 	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 }

@@ -180,17 +170,17 @@ int eeprom_write_enable (unsigned dev_ad
 		switch (state) {
 		case 1:
 			/* Enable write access, clear bit GPIO_SINT2. */
-			out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
+			out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
 			state = 0;
 			break;
 		case 0:
 			/* Disable write access, set bit GPIO_SINT2. */
-			out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
+			out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
 			state = 0;
 			break;
 		default:
 			/* Read current status back. */
-			state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
+			state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP));
 			break;
 		}
 	}

@@ -235,19 +225,6 @@ U_BOOT_CMD(eepwren,	2,	0,	do_eep_wren,
 
 /* ------------------------------------------------------------------------- */
 
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
-	nand_probe(CFG_NAND_BASE);
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
-}
-#endif
-
 void reset_phy(void)
 {
 #ifdef CONFIG_LXT971_NO_SLEEP

board/esd/hh405/Makefile +4 -1

index ce7876c..0e5e57a 100644
@@ -28,7 +28,10 @@ endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
+	../common/auto_update.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/esd/hh405/hh405.c +1 ~~-21~~

index ea344c0..67b5d54 100644
@@ -5,7 +5,7 @@
  * (C) Copyright 2005
  * Stefan Roese, DENX Software Engineering, sr at denx.de.
  *
- * (C) Copyright 2006
+ * (C) Copyright 2006-2007
  * Matthias Fuchs, esd GmbH, matthias.fuchs at esd-electronics.com
  *
  * See file CREDITS for list of people who contributed to this

@@ -477,12 +477,6 @@ int misc_init_r (void)
 	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
 
 	/*
-	 * Set NAND-FLASH GPIO signals to default
-	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
-	/*
 	 * Reset touch-screen controller
 	 */
 	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_TOUCH_RST);

@@ -690,20 +684,6 @@ void ide_set_reset(int on)
 #endif /* CONFIG_IDE_RESET */
 
 
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
-	nand_probe(CFG_NAND_BASE);
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
-}
-#endif
-
-
 #if defined(CFG_EEPROM_WREN)
 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
  *         <state>     -1: deliver current state

board/esd/hub405/Makefile +3 -1

index 4d75868..308f752 100644
@@ -28,7 +28,9 @@ endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o flash.o ../common/misc.o
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/esd/hub405/hub405.c +0 ~~-34~~

index 1e0accb..25c8068 100644
@@ -153,12 +153,6 @@ int misc_init_r (void)
 	out32(GPIO0_OR, val);
 
 	/*
-	 * Set NAND-FLASH GPIO signals to default
-	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
-	/*
 	 * check board type and setup AP power
 	 */
 	str = getenv("bd_type"); /* this is only set on non prototype hardware */

@@ -242,33 +236,5 @@ long int initdram (int board_type)
 	mtdcr(memcfga, mem_mb0cf);
 	val = mfdcr(memcfgd);
 
-#if 0
-	printf("\nmb0cf=%x\n", val); /* test-only */
-	printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
 	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 }
-
-
-int testdram (void)
-{
-	/* TODO: XXX XXX XXX */
-	printf ("test: 16 MB - ok\n");
-
-	return (0);
-}
-
-
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
-	nand_probe(CFG_NAND_BASE);
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
-}
-#endif

board/esd/plu405/Makefile +4 -1

index ce7876c..0e5e57a 100644
@@ -28,7 +28,10 @@ endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
+	../common/auto_update.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/esd/plu405/plu405.c +9 ~~-47~~

100 lines not on this page · raw message

board/esd/voh405/Makefile +3 -1

index 4d75868..308f752 100644
@@ -28,7 +28,9 @@ endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o flash.o ../common/misc.o
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/esd/voh405/voh405.c +0 ~~-20~~

index 22995b5..2857a0b 100644
@@ -195,12 +195,6 @@ int misc_init_r (void)
 	udelay(1000); /* wait 1ms */
 
 	/*
-	 * Set NAND-FLASH GPIO signals to default
-	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
-	/*
 	 * Enable interrupts in exar duart mcr[3]
 	 */
 	*duart0_mcr = 0x08;

@@ -340,17 +334,3 @@ void ide_set_reset(int on)
 	}
 }
 #endif /* CONFIG_IDE_RESET */
-
-
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
-	nand_probe(CFG_NAND_BASE);
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
-}
-#endif

board/esd/wuh405/Makefile +3 -1

index 4d75868..308f752 100644
@@ -28,7 +28,9 @@ endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o flash.o ../common/misc.o
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/esd/wuh405/wuh405.c +0 ~~-33~~

index 5a1a3f3..0b53062 100644
@@ -170,12 +170,6 @@ int misc_init_r (void)
 	udelay(1000); /* wait 1ms */
 
 	/*
-	 * Set NAND-FLASH GPIO signals to default
-	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
-	/*
 	 * Enable interrupts in exar duart mcr[3]
 	 */
 	*duart0_mcr = 0x08;

@@ -218,35 +212,8 @@ long int initdram (int board_type)
 	mtdcr(memcfga, mem_mb0cf);
 	val = mfdcr(memcfgd);
 
-#if 0
-	printf("\nmb0cf=%x\n", val); /* test-only */
-	printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
 	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 }
 
 /* ------------------------------------------------------------------------- */
 
-int testdram (void)
-{
-	/* TODO: XXX XXX XXX */
-	printf ("test: 16 MB - ok\n");
-
-	return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
-	nand_probe(CFG_NAND_BASE);
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
-}
-#endif

include/configs/ASH405.h +12 ~~-31~~

60 lines not on this page · raw message

include/configs/CMS700.h +9 ~~-30~~

index 1cca285..9695211 100644
@@ -81,8 +81,6 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
-#define CFG_NAND_LEGACY
-
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

@@ -148,34 +146,15 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN	0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE }
+#define NAND_MAX_CHIPS          1
+#define CFG_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US	25
+
+#define CFG_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
+#define CFG_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
+#define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
+#define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 
 #define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */

include/configs/HH405.h +9 ~~-30~~

index dc40ebc..f36777a 100644
@@ -130,8 +130,6 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
-#define CFG_NAND_LEGACY
-
 #undef  CONFIG_BZIP2	 /* include support for bzip2 compressed images */
 #undef  CONFIG_WATCHDOG			/* watchdog disabled		*/

@@ -198,34 +196,15 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 	0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE  (0x80000000 >> 1)  /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2)  /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3)  /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4)  /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE }
+#define NAND_MAX_CHIPS          1
+#define CFG_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US	25
+
+#define CFG_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
+#define CFG_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
+#define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
+#define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 
 #define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */

include/configs/HUB405.h +9 ~~-30~~

index f84e356..88cc6a4 100644
@@ -135,36 +135,15 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN	0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE }
+#define NAND_MAX_CHIPS          1
+#define CFG_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US	25
+
+#define CFG_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
+#define CFG_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
+#define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
+#define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 
 #define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */

include/configs/PLU405.h +9 ~~-48~~

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include/configs/VOH405.h +9 ~~-30~~

index 96f3d26..abd1ef4 100644
@@ -141,36 +141,15 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN	0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE }
+#define NAND_MAX_CHIPS          1
+#define CFG_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US	25
+
+#define CFG_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
+#define CFG_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
+#define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
+#define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 
 #define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */

include/configs/WUH405.h +10 ~~-32~~

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