rt2x00: Put rf register value detection in function

index a69e0f6..55975d3 100644
@@ -330,22 +330,37 @@ static void rt2400pci_config_type(struct rt2x00_dev *rt2x00dev, int type)
 	rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 }
 
+static void rt2400pci_get_rf_vals(struct rt2x00_dev *rt2x00dev,
+	const int value, const int channel, struct rf_reg *reg)
+{
+	reg->rf1 = 0x00022058;
+	reg->rf2 = value;
+	if (rt2x00_rf(&rt2x00dev->chip, RF2420))
+		reg->rf3 = 0x00000111;
+	else
+		reg->rf3 = 0x00000101;
+	reg->rf4 = 0;
+}
+
 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
 	const int value, const int channel, const int txpower)
 {
-	u32 rf1 = rt2x00dev->rf1;
-	u32 rf2 = value;
-	u32 rf3 = rt2x00dev->rf3;
+	struct rf_reg reg;
+
+	/*
+	 * Fill rf_reg structure.
+	 */
+	rt2400pci_get_rf_vals(rt2x00dev, value, channel, &reg);
 
 	/*
 	 * Switch on tuning bits.
 	 */
-	rt2x00_set_field32(&rf1, RF1_TUNER, 1);
-	rt2x00_set_field32(&rf3, RF3_TUNER, 1);
+	rt2x00_set_field32(&reg.rf1, RF1_TUNER, 1);
+	rt2x00_set_field32(&reg.rf3, RF3_TUNER, 1);
 
-	rt2400pci_rf_write(rt2x00dev, rf1);
-	rt2400pci_rf_write(rt2x00dev, rf2);
-	rt2400pci_rf_write(rt2x00dev, rf3);
+	rt2400pci_rf_write(rt2x00dev, reg.rf1);
+	rt2400pci_rf_write(rt2x00dev, reg.rf2);
+	rt2400pci_rf_write(rt2x00dev, reg.rf3);
 
 	/*
 	 * RF2420 chipset don't need any additional actions.

@@ -358,38 +373,38 @@ static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
 	 * reference clock rate to activate auto_tune.
 	 * After that we set the value back to the correct channel.
 	 */
-	rt2400pci_rf_write(rt2x00dev, rf1);
+	rt2400pci_rf_write(rt2x00dev, reg.rf1);
 	rt2400pci_rf_write(rt2x00dev, 0x000c2a32);
-	rt2400pci_rf_write(rt2x00dev, rf3);
+	rt2400pci_rf_write(rt2x00dev, reg.rf3);
 
 	msleep(1);
 
-	rt2400pci_rf_write(rt2x00dev, rf1);
-	rt2400pci_rf_write(rt2x00dev, rf2);
-	rt2400pci_rf_write(rt2x00dev, rf3);
+	rt2400pci_rf_write(rt2x00dev, reg.rf1);
+	rt2400pci_rf_write(rt2x00dev, reg.rf2);
+	rt2400pci_rf_write(rt2x00dev, reg.rf3);
 
 	msleep(1);
 
 	/*
 	 * Switch off tuning bits.
 	 */
-	rt2x00_set_field32(&rf1, RF1_TUNER, 0);
-	rt2x00_set_field32(&rf3, RF3_TUNER, 0);
+	rt2x00_set_field32(&reg.rf1, RF1_TUNER, 0);
+	rt2x00_set_field32(&reg.rf3, RF3_TUNER, 0);
 
-	rt2400pci_rf_write(rt2x00dev, rf1);
-	rt2400pci_rf_write(rt2x00dev, rf3);
+	rt2400pci_rf_write(rt2x00dev, reg.rf1);
+	rt2400pci_rf_write(rt2x00dev, reg.rf3);
 
 	/*
 	 * Update rf fields
 	 */
-	rt2x00dev->rf1 = rf1;
-	rt2x00dev->rf2 = rf2;
-	rt2x00dev->rf3 = rf3;
+	rt2x00dev->rf1 = reg.rf1;
+	rt2x00dev->rf2 = reg.rf2;
+	rt2x00dev->rf3 = reg.rf3;
 
 	/*
 	 * Clear false CRC during channel switch.
 	 */
-	rt2x00pci_register_read(rt2x00dev, CNT0, &rf1);
+	rt2x00pci_register_read(rt2x00dev, CNT0, &reg.rf1);
 }
 
 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)

@@ -1415,15 +1430,6 @@ static void rt2400pci_init_hw_mode(struct rt2x00_dev *rt2x00dev)
 		rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0));
 
 	/*
-	 * Set device specific, but channel independent RF values.
-	 */
-	rt2x00dev->rf1 = 0x00022058;
-	if (rt2x00_rf(&rt2x00dev->chip, RF2420))
-		rt2x00dev->rf3 = 0x00000111;
-	else
-		rt2x00dev->rf3 = 0x00000101;
-
-	/*
 	 * Convert tx_power array in eeprom.
 	 */
 	txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);

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index cca9160..eb96d07 100644
@@ -343,6 +343,17 @@ struct rt2x00_chip {
 };
 
 /*
+ * RF register collection structure
+ * This structure contains the value for all RF register words.
+ */
+struct rf_reg {
+	u32 rf1;
+	u32 rf2;
+	u32 rf3;
+	u32 rf4;
+};
+
+/*
  * data_desc
  * Each data entry also contains a descriptor which is used by the
  * device to determine what should be done with the packet and

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