ssb-chipcommon: Add function to get processor clock
PATCH 1/1 ssb-chipcommon: Add function to get processor clock
From: Aurelien Jarno <[email protected]>
The patch below (against 2.6.23-rc1-mm1) adds a new function to get the processor clock. It originally comes from the OpenWrt patches.
drivers/ssb/driver_chipcommon.c +24 -0
@@ -264,6 +264,30 @@ssb_chipco_set_clockmode (cc,SSB_CLKMODE_FAST ); } +/* Get the processor clock */ +void ssb_chipco_get_clockcpu (struct ssb_chipcommon *cc, +u32 *plltype,u32 *n,u32 *m) +{ + *n =chipco_read32 (cc,SSB_CHIPCO_CLOCK_N ); + *plltype = (cc->capabilities &SSB_CHIPCO_CAP_PLLT ); +switch (*plltype) { +case SSB_PLLTYPE_2 : +case SSB_PLLTYPE_4 : +case SSB_PLLTYPE_6 : +case SSB_PLLTYPE_7 : + *m =chipco_read32 (cc,SSB_CHIPCO_CLOCK_MIPS ); +break ; +case SSB_PLLTYPE_3 : +/* 5350 uses m2 to control mips */ + *m =chipco_read32 (cc,SSB_CHIPCO_CLOCK_M2 ); +break ; +default : + *m =chipco_read32 (cc,SSB_CHIPCO_CLOCK_SB ); +break ; + } +} + +/* Get the bus clock */ void ssb_chipco_get_clockcontrol (struct ssb_chipcommon *cc,u32 *plltype,u32 *n,u32 *m) {
include/linux/ssb/ssb_driver_chipcommon.h +2 -0
@@ -364,6 +364,8 @@extern void ssb_chipco_suspend (struct ssb_chipcommon *cc,pm_message_t state);extern void ssb_chipco_resume (struct ssb_chipcommon *cc); +extern void ssb_chipco_get_clockcpu (struct ssb_chipcommon *cc, +u32 *plltype,u32 *n,u32 *m);extern void ssb_chipco_get_clockcontrol (struct ssb_chipcommon *cc,u32 *plltype,u32 *n,u32 *m); extern void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
Signature · 1 line
Greetings Michael.
Quoted 27 lines · On Wed, 1 Aug 2007 00:11:56 +0200 Michael Buesch <[email protected]> wrote:
From: Aurelien Jarno <[email protected]>
The patch below (against 2.6.23-rc1-mm1) adds a new function to get the processor clock. It originally comes from the OpenWrt patches.
Cc Felix Fietkau <[email protected]>Signed-off-by Aurelien Jarno <[email protected]>Signed-off-by Michael Buesch <[email protected]>drivers/ssb/driver_chipcommon.c +12
-0@@ -264,6 +264,30 @@ssb_chipco_set_clockmode (cc,SSB_CLKMODE_FAST ); } +/* Get the processor clock */ +void ssb_chipco_get_clockcpu (struct ssb_chipcommon *cc, +u32 *plltype,u32 *n,u32 *m) +{ + *n =chipco_read32 (cc,SSB_CHIPCO_CLOCK_N ); + *plltype = (cc->capabilities &SSB_CHIPCO_CAP_PLLT ); +switch (*plltype) { +case SSB_PLLTYPE_2 : +case SSB_PLLTYPE_4 : +case SSB_PLLTYPE_6 : +case SSB_PLLTYPE_7 : + *m =chipco_read32 (cc,SSB_CHIPCO_CLOCK_MIPS );
drivers/ssb/driver_chipcommon.c line 288
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drivers/ssb/driver_chipcommon.c +10
-0+break ; +case SSB_PLLTYPE_3 : +/* 5350 uses m2 to control mips */ + *m =chipco_read32 (cc,SSB_CHIPCO_CLOCK_M2 ); +break ; +default : + *m =chipco_read32 (cc,SSB_CHIPCO_CLOCK_SB ); +break ; + } +}
Please indent the body of switch statements one tabstop less than this.
include/linux/ssb/ssb_driver_chipcommon.h line 368
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drivers/ssb/driver_chipcommon.c +1
-0+/* Get the bus clock */ void ssb_chipco_get_clockcontrol (struct ssb_chipcommon *cc,u32 *plltype,u32 *n,u32 *m) {include/linux/ssb/ssb_driver_chipcommon.h +2
-0@@ -364,6 +364,8 @@extern void ssb_chipco_suspend (struct ssb_chipcommon *cc,pm_message_t state);extern void ssb_chipco_resume (struct ssb_chipcommon *cc); +extern void ssb_chipco_get_clockcpu (struct ssb_chipcommon *cc, +u32 *plltype,u32 *n,u32 *m);
But it has no callers?
Quoted 34 lines · On Thursday 02 August 2007 00:06:11 Andrew Morton wrote:
Quoted 31 lines · On Wed, 1 Aug 2007 00:11:56 +0200 Michael Buesch <[email protected]> wrote:
From: Aurelien Jarno <[email protected]>
The patch below (against 2.6.23-rc1-mm1) adds a new function to get the processor clock. It originally comes from the OpenWrt patches.
Cc Felix Fietkau <[email protected]>Signed-off-by Aurelien Jarno <[email protected]>Signed-off-by Michael Buesch <[email protected]>drivers/ssb/driver_chipcommon.c +16
-0@@ -264,6 +264,30 @@ssb_chipco_set_clockmode (cc,SSB_CLKMODE_FAST ); } +/* Get the processor clock */ +void ssb_chipco_get_clockcpu (struct ssb_chipcommon *cc, +u32 *plltype,u32 *n,u32 *m) +{ + *n =chipco_read32 (cc,SSB_CHIPCO_CLOCK_N ); + *plltype = (cc->capabilities &SSB_CHIPCO_CAP_PLLT ); +switch (*plltype) { +case SSB_PLLTYPE_2 : +case SSB_PLLTYPE_4 : +case SSB_PLLTYPE_6 : +case SSB_PLLTYPE_7 : + *m =chipco_read32 (cc,SSB_CHIPCO_CLOCK_MIPS ); +break ; +case SSB_PLLTYPE_3 : +/* 5350 uses m2 to control mips */ + *m =chipco_read32 (cc,SSB_CHIPCO_CLOCK_M2 );
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drivers/ssb/driver_chipcommon.c line 288
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drivers/ssb/driver_chipcommon.c +6
-0+break ; +default : + *m =chipco_read32 (cc,SSB_CHIPCO_CLOCK_SB ); +break ; + } +}Please indent the body of switch statements one tabstop less than this.
Ok, please resend, Aurelien :)
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drivers/ssb/driver_chipcommon.c +1
-0+/* Get the bus clock */ void ssb_chipco_get_clockcontrol (struct ssb_chipcommon *cc,u32 *plltype,u32 *n,u32 *m) {include/linux/ssb/ssb_driver_chipcommon.h +0
-0@@ -364,6 +364,8 @@extern void ssb_chipco_suspend (struct ssb_chipcommon *cc,pm_message_t state);extern void ssb_chipco_resume (struct ssb_chipcommon *cc);
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include/linux/ssb/ssb_driver_chipcommon.h line 368
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include/linux/ssb/ssb_driver_chipcommon.h +2
-0+extern void ssb_chipco_get_clockcpu (struct ssb_chipcommon *cc, +u32 *plltype,u32 *n,u32 *m);But it has no callers?
The callers are in the bcm47xx arch code. We are going to merge that, too. This patch is part of the merge.
We can't (and shouldn't) merge it all at once.
There are still a few dirty hacks in there that won't get accepted, yet.
Signature · 1 line
Greetings Michael.
Michael Buesch a =E9crit :
Quoted 7 lines · On Thursday 02 August 2007 00:06:11 Andrew Morton wrote:
Quoted 6 lines
Quoted 3 lines · On Wed, 1 Aug 2007 00:11:56 +0200 Michael Buesch <[email protected]> wrote:
From: Aurelien Jarno <[email protected]>
The patch below (against 2.6.23-rc1-mm1) adds a new function to get=
the=20
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processor clock. It originally comes from the OpenWrt patches.
Cc Felix Fietkau <[email protected]>Signed-off-by Aurelien Jarno <[email protected]>Signed-off-by Michael Buesch <[email protected]>---
a/drivers/ssb/driver_chipcommon.c2007-07-14 21:05:44.000000000=
+0200
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+++
b/drivers/ssb/driver_chipcommon.c2007-07-14 21:22:04.000000000=
+0200
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drivers/ssb/driver_chipcommon.c +0
-0@@ -264,6 +264,30 @@ssb_chipco_set_clockmode (cc,SSB_CLKMODE_FAST ); }=20
drivers/ssb/driver_chipcommon.c +15
-0+/* Get the processor clock */ +void ssb_chipco_get_clockcpu (struct ssb_chipcommon *cc, +u32 *plltype,u32 *n,u32 *m) +{ + *n =3D chipco_read32(cc, SSB_CHIPCO_CLOCK_N); + *plltype =3D (cc->capabilities &SSB_CHIPCO_CAP_PLLT ); +switch (*plltype) { +case SSB_PLLTYPE_2 : +case SSB_PLLTYPE_4 : +case SSB_PLLTYPE_6 : +case SSB_PLLTYPE_7 : + *m =3D chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS); +break ; +case SSB_PLLTYPE_3 : +/* 5350 uses m2 to control mips */
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drivers/ssb/driver_chipcommon.c line 288
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drivers/ssb/driver_chipcommon.c +7
-0+ *m =3D chipco_read32(cc, SSB_CHIPCO_CLOCK_M2); +break ; +default : + *m =3D chipco_read32(cc, SSB_CHIPCO_CLOCK_SB); +break ; + } +}Please indent the body of switch statements one tabstop less than th=
is.
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=20
Ok, please resend, Aurelien :)
It looks like Andrew took care of that.
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drivers/ssb/driver_chipcommon.c
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drivers/ssb/driver_chipcommon.c +1
-1+/* Get the bus clock */ void ssb_chipco_get_clockcontrol (struct ssb_chipcommon *cc,u32 *plltype,u32 *n,u32 *m) { --- a/include/linux/ssb/ssb_driver_chipcommon.h 2007-07-14 21:05:44=
=2E000000000 +0200
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+++
b/include/linux/ssb/ssb_driver_chipcommon.h2007-07-14 21:17:28=
=2E000000000 +0200
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Review line 364
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(quoted diff) +0
-0@@ -364,6 +364,8 @@ extern void ssb_chipco_suspend(struct ssb_chipcommon *cc, pm_messa=
ge_t state);
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include/linux/ssb/ssb_driver_chipcommon.h +0
-0extern void ssb_chipco_resume (struct ssb_chipcommon *cc);=20
include/linux/ssb/ssb_driver_chipcommon.h +2
-0+extern void ssb_chipco_get_clockcpu (struct ssb_chipcommon *cc, +u32 *plltype,u32 *n,u32 *m);
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But it has no callers?
=20
The callers are in the bcm47xx arch code. We are going to merge that, too. This patch is part of the merge.
We can't (and shouldn't) merge it all at once.
There are still a few dirty hacks in there that won't get accepted, y=
et.
Yep the merge of the bcm47xx is on my TODO list, but I want to finish the SSB parts first. I hope to finish that before the end of this week-= end.
About the bcm47xx arch code, my plan is to merge first a very simple version that allow the machine to boot, but without support for CFE.
--=20
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' [email protected] | [email protected] `- people.debian.org/~aurel32 | www.aurel32.net
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Quoted 6 lines · On Thursday 02 August 2007 11:12:30 Aurelien Jarno wrote:
Yep the merge of the bcm47xx is on my TODO list, but I want to finish the SSB parts first. I hope to finish that before the end of this week-end.
About the bcm47xx arch code, my plan is to merge first a very simple version that allow the machine to boot, but without support for CFE.
There are also mipscore patches in openwrt that need to get merged upstream. Do you take care of these, too?
Signature · 1 line
Greetings Michael.
Michael Buesch a =E9crit :
Quoted 2 lines · On Thursday 02 August 2007 11:12:30 Aurelien Jarno wrote:
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Yep the merge of the bcm47xx is on my TODO list, but I want to finis=
h
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the SSB parts first. I hope to finish that before the end of this we=
ek-end.
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About the bcm47xx arch code, my plan is to merge first a very simple version that allow the machine to boot, but without support for CFE.
=20
There are also mipscore patches in openwrt that need to get merged up=
stream.
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Do you take care of these, too?
Yep I am currently working on that.
--=20
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' [email protected] | [email protected] `- people.debian.org/~aurel32 | www.aurel32.net
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