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Fix MPC8544DS PCIe3 scsi.

PATCH New Ed Swarthout 6 participants 13 messages Aug 20, 2007 – Aug 30, 2007

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Ed Swarthout

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#0 lore raw

PATCH 1/1 Fix MPC8544DS PCIe3 scsi.

From: Ed Swarthout <[email protected]>

Increase PCIe 3 Memory region to 8M to fix scsi invalid port number:

SCSI: scanning bus for devices...
Invaild port number 1
Invaild port number 2
Invaild port number 3

Signed-off-by Ed Swarthout <[email protected]>

---

d64ee908 reduced PCIe 3 region by too much.
With this fix I get 0xb010c000 assigned to bar5.

 board/freescale/mpc8544ds/init.S |    2 +-
 include/configs/MPC8544DS.h      |    4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)
board/freescale/mpc8544ds/init.S +1 -1
index 900c368..ca1b5d5 100644
@@ -237,6 +237,6 @@ law_entry:
 
 	/* contains both PCIE3 MEM & IO space */
 	.long	(CFG_PCIE3_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_2M)
+	.long	LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_16M)
 4:
 	entry_end
include/configs/MPC8544DS.h +2 -2
index 746f360..ba5aa00 100644
@@ -308,9 +308,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /* controller 3, direct to uli, tgtid 3, Base address b000 */
 #define CFG_PCIE3_MEM_BASE	0xb0000000
 #define CFG_PCIE3_MEM_PHYS	CFG_PCIE3_MEM_BASE
-#define CFG_PCIE3_MEM_SIZE	0x00100000	/* 1M */
+#define CFG_PCIE3_MEM_SIZE	0x00800000	/* 8M of 16M LAW */
 #define CFG_PCIE3_IO_BASE	0x00000000
-#define CFG_PCIE3_IO_PHYS	0xb0100000	/* reuse mem LAW */
+#define CFG_PCIE3_IO_PHYS	0xb0800000	/* reuse mem LAW */
 #define CFG_PCIE3_IO_SIZE	0x00100000	/* 1M */
 
 #if defined(CONFIG_PCI)
Signature · 1 line
1.5.3.rc5.18.ga85e4
#1 lore raw

PATCH 1/1 Fix MPC8544DS PCIe3 scsi.

Quoted 10 lines · Ed Swarthout

From: Ed Swarthout <[email protected]>

Increase PCIe 3 Memory region to 8M to fix scsi invalid port number:

SCSI: scanning bus for devices...
Invaild port number 1
Invaild port number 2
Invaild port number 3

Signed-off-by Ed Swarthout <[email protected]>
Quoted 8 lines

---

d64ee908 reduced PCIe 3 region by too much.
With this fix I get 0xb010c000 assigned to bar5.

 board/freescale/mpc8544ds/init.S |    2 +-
 include/configs/MPC8544DS.h      |    4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

I don't understand why this is needed. It seems like something more fundamental in the u-boot allocator if it can't handle all the devices in 1M of memory space. No devices memory space requirement is greater than 4k and there are only 5 or 6 of them.

- k

#2 lore raw

PATCH 1/1 Fix MPC8544DS PCIe3 scsi.

Quoted 5 lines · Kumar Gala

I don't understand why this is needed. It seems like something more fundamental in the u-boot allocator if it can't handle all the devices in 1M of memory space. No devices memory space requirement is greater than 4k and there are only 5 or 6 of them.

This 'hack' seems to workaround the issue in slightly better way. Not sure if we can do anything better.

The problem is pciauto_setup_device() getting called from fsl_pci_init.c is allocating memory space it doesn't need.

- k

drivers/fsl_pci_init.c +4 -0
index 1084dc6..193343b 100644
@@ -54,6 +54,7 @@ fsl_pci_init(struct pci_controller *hose)
 	u8 temp8;
 	int r;
 	int bridge;
+	unsigned long bus_lower_temp;
 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr;
 	pci_dev_t dev = PCI_BDF(busno,0,0);
 

@@ -131,8 +132,11 @@ fsl_pci_init(struct pci_controller *hose)
 	}
 
 	/* Call setup to allocate PCSRBAR window */
+	bus_lower_temp = hose->pci_mem->bus_lower;
 	pciauto_setup_device(hose, dev, 1, hose->pci_mem,
 			     hose->pci_prefetch, hose->pci_io);
+	hose->pci_mem->bus_lower = bus_lower_temp;
+
 #ifndef CONFIG_PCI_NOSCAN
 	printf ("               Scanning PCI bus %02x\n", hose->current_busno);
 	hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno);
drivers/pci_auto.c +0 -0
author
#3 lore raw

PATCH 1/1 fsl_pci_init - Remove self PCSRBAR allocation

From: Ed Swarthout <[email protected]>

CPU physical address space was being wasted by allocating a PCSRBAR PCI inbound region to it's memory space.

As a rule, PCSRBAR should be left alone since it does not affect transactions from self and other masters may have changed it.

Signed-off-by Ed Swarthout <[email protected]>

---

Was: {PATCH] Fix MPC8544DS PCIe3 scsi.

This fixes the MPC8544DS scsi error:

SCSI: scanning bus for devices...
Invaild port number 1
Invaild port number 2
Invaild port number 3

when not enough PCIe3 memory space is available for allocation.

This replaces k's temp hack.

 drivers/fsl_pci_init.c |    9 +++++++--
 1 files changed, 7 insertions(+), 2 deletions(-)
drivers/fsl_pci_init.c +7 -2
index 1084dc6..3a13eea 100644
@@ -130,9 +130,14 @@ fsl_pci_init(struct pci_controller *hose)
 
 	}
 
-	/* Call setup to allocate PCSRBAR window */
-	pciauto_setup_device(hose, dev, 1, hose->pci_mem,
+	/* Use generic setup_device to initialize standard pci regs,
+	 * but do not allocate any windows since any BAR found (such
+	 * as PCSRBAR) is not in this cpu's memory space.
+	 */
+
+	pciauto_setup_device(hose, dev, 0, hose->pci_mem,
 			     hose->pci_prefetch, hose->pci_io);
+
 #ifndef CONFIG_PCI_NOSCAN
 	printf ("               Scanning PCI bus %02x\n", hose->current_busno);
 	hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno);
Signature · 1 line
1.5.3.rc5.18.ga85e4
Applied
#5 lore raw

PATCH 1/1 fsl_pci_init - Remove self PCSRBAR allocation

In reply to Ed Swarthout
Quoted 9 lines · In message <[email protected]> you wrote:

From: Ed Swarthout <[email protected]>

CPU physical address space was being wasted by allocating a PCSRBAR PCI inbound region to it's memory space.

As a rule, PCSRBAR should be left alone since it does not affect transactions from self and other masters may have changed it.

Signed-off-by Ed Swarthout <[email protected]>

Applied, thanks.

Best regards,

Wolfgang Denk

Signature · 5 lines
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The only way to learn a new programming language is by  writing  pro-
grams in it.                                        - Brian Kernighan
#6 lore raw

PATCH 1/1 Fix MPC8544DS PCIe3 scsi.

In reply to Kumar Gala

drivers/fsl_pci_init.c

Quoted 19 lines · In message <[email protected]> you wrote:
Quoted 5 lines · Kumar Gala

I don't understand why this is needed. It seems like something more fundamental in the u-boot allocator if it can't handle all the devices in 1M of memory space. No devices memory space requirement is greater than 4k and there are only 5 or 6 of them.

This 'hack' seems to workaround the issue in slightly better way. Not sure if we can do anything better.

The problem is pciauto_setup_device() getting called from fsl_pci_init.c is allocating memory space it doesn't need.

- k

drivers/fsl_pci_init.c +0 -0
index 1084dc6..193343b 100644

...

What's the state of this? Will it go into the MPC85xx custodian tree?

Best regards,

Wolfgang Denk

Signature · 6 lines
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
If a man had a child who'd gone  anti-social,  killed  perhaps,  he'd
still tend to protect that child.
	-- McCoy, "The Ultimate Computer", stardate 4731.3
#7 lore raw

PATCH 1/1 Fix MPC8544DS PCIe3 scsi.

Quoted 8 lines · Wolfgang Denk

In message <[email protected]>

drivers/fsl_pci_init.c

Quoted 4 lines
drivers/fsl_pci_init.c +0 -0
index 1084dc6..193343b 100644

...

What's the state of this? Will it go into the MPC85xx custodian tree?

Yes, I will send you a pull request tonight, assuming all goes well.

Andy

#8 lore raw

PATCH 1/1 Fix MPC8544DS PCIe3 scsi.

In reply to Wolfgang Denk
Quoted 6 lines · Wolfgang Denk

drivers/fsl_pci_init.c

Quoted 3 lines
drivers/fsl_pci_init.c +0 -0
index 1084dc6..193343b 100644

...

What's the state of this? Will it go into the MPC85xx custodian tree?

No, please discard. It is superseeded with:

Re: [U-Boot-Users] [PATCH] fsl_pci_init - Remove self PCSRBAR allocation

which you have just applied.

Thanks,
-EdS

#9 lore raw

PATCH 1/1 Fix MPC8544DS PCIe3 scsi.

In reply to Wolfgang Denk
Quoted 19 lines · Wolfgang Denk

In message <Pine.LNX.

Quoted 17 lines · 4.64.0708200942240.25897 at blarg.am.freescale.net> you wrote:
Quoted 5 lines · Kumar Gala

I don't understand why this is needed. It seems like something more fundamental in the u-boot allocator if it can't handle all the devices in 1M of memory space. No devices memory space requirement is greater than 4k and there are only 5 or 6 of them.

This 'hack' seems to workaround the issue in slightly better way. Not
sure if we can do anything better.

The problem is pciauto_setup_device() getting called from fsl_pci_init.c
is allocating memory space it doesn't need.

- k

Quoted 7 lines

drivers/fsl_pci_init.c

Quoted 4 lines
drivers/fsl_pci_init.c +0 -0
index 1084dc6..193343b 100644

...

What's the state of this? Will it go into the MPC85xx custodian tree?

This was a hack, Ed's version "fsl_pci_init - Remove self PCSRBAR allocation" is cleaner and show replace this version that happened to go in via the MPC85xx custodian tree.

- k

#10 lore raw

PATCH 1/1 Revert "Fix MPC8544DS PCIe3 scsi."

This reverts commit 9468e680.
Commit 16e23c3f5da removing allocation of PCSRBAR is sufficient.

Signed-off-by Ed Swarthout <[email protected]>
---
 drivers/fsl_pci_init.c |    4 +---
 1 files changed, 1 insertions(+), 3 deletions(-)
drivers/fsl_pci_init.c +1 -3
index a4ce458..3a13eea 100644
@@ -54,7 +54,6 @@ fsl_pci_init(struct pci_controller *hose)
 	u8 temp8;
 	int r;
 	int bridge;
-	unsigned long bus_lower_temp;
 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr;
 	pci_dev_t dev = PCI_BDF(busno,0,0);
 

@@ -135,10 +134,9 @@ fsl_pci_init(struct pci_controller *hose)
 	 * but do not allocate any windows since any BAR found (such
 	 * as PCSRBAR) is not in this cpu's memory space.
 	 */
-	bus_lower_temp = hose->pci_mem->bus_lower;
+
 	pciauto_setup_device(hose, dev, 0, hose->pci_mem,
 			     hose->pci_prefetch, hose->pci_io);
-	hose->pci_mem->bus_lower = bus_lower_temp;
 
 #ifndef CONFIG_PCI_NOSCAN
 	printf ("               Scanning PCI bus %02x\n", hose->current_busno);
Signature · 1 line
1.5.3.rc6.63.gf7c18
Applied
#11 lore raw

PATCH 1/1 Revert "Fix MPC8544DS PCIe3 scsi."

Quoted 4 lines · In message <[email protected]> you wrote:

This reverts commit 9468e680.
Commit 16e23c3f5da removing allocation of PCSRBAR is sufficient.

Signed-off-by Ed Swarthout <[email protected]>

Applied, thanks.

Best regards,

Wolfgang Denk

Signature · 4 lines
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Lack of skill dictates economy of style.                - Joey Ramone
#12 lore raw

PATCH 1/1 Fix MPC8544DS PCIe3 scsi.

In reply to Ed Swarthout

Dear Andy,

Quoted 10 lines · in message <[email protected]> Ed…

From: Ed Swarthout <[email protected]>

Increase PCIe 3 Memory region to 8M to fix scsi invalid port number:

SCSI: scanning bus for devices...
Invaild port number 1
Invaild port number 2
Invaild port number 3

Signed-off-by Ed Swarthout <[email protected]>

What about this one? Will you send me a pull request for the MPC85xx tree soon, or should I pick this up direclty, or should I ignore it?

Best regards,

Wolfgang Denk

Signature · 7 lines
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
I don't mind criticism. You know me. I've  never  been  one  to  take
offence  at  criticism. No one could say I'm the sort to take offence
at criticism -- Not twice, anyway. Not without blowing bubbles.
                                  - Terry Pratchett, _Witches Abroad_