mpc8568e_mds: UCC0's PHY is at 0x7, not 0x1
Subsystems (2)
PATCH 1/1 mpc8568e_mds: UCC0's PHY is at 0x7, not 0x1
There was probably a typo in the documentation, or it's hw errata. Recent u-boot also using 0x7.
Signed-off-by Anton Vorontsov <[email protected]>
--- arch/powerpc/boot/dts/mpc8568mds.dts | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-)
arch/powerpc/boot/dts/mpc8568mds.dts +4 -4
@@ -97,10 +97,10 @@ device_type = "mdio"; compatible = "gianfar"; reg = <24520 20>; - phy0: ethernet-phy@0 { + phy0: ethernet-phy@7 { interrupt-parent = <&mpic>; interrupts = <1 1>; - reg = <0>; + reg = <7>; device_type = "ethernet-phy"; }; phy1: ethernet-phy@1 {
@@ -417,10 +417,10 @@ /* These are the same PHYs as on * gianfar's MDIO bus */ - qe_phy0: ethernet-phy@00 { + qe_phy0: ethernet-phy@07 { interrupt-parent = <&mpic>; interrupts = <1 1>; - reg = <0>; + reg = <7>; device_type = "ethernet-phy"; }; qe_phy1: ethernet-phy@01 {
Signature · 1 line
1.5.0.6