Fix QEIC->MPIC cascading

set_irq_chained_handler overwrites MPIC's handle_irq function (handle_fasteoi_irq) thus MPIC never gets eoi event from the cascaded IRQ. This situation hangs MPIC on MPC8568E.

Patch adds flow level "end" handler to the MPIC, and QEIC calls it when QEIC's interrupt processing finished.

---
 arch/powerpc/sysdev/mpic.c         |    3 +++
 arch/powerpc/sysdev/qe_lib/qe_ic.c |    6 ++++++
 2 files changed, 9 insertions(+), 0 deletions(-)

index 8de29f2..bee2d5b 100644
@@ -846,6 +846,7 @@ static struct irq_chip mpic_irq_chip = {
 	.mask		= mpic_mask_irq,
 	.unmask		= mpic_unmask_irq,
 	.eoi		= mpic_end_irq,
+	.end		= mpic_end_irq,
 	.set_type	= mpic_set_irq_type,
 };
 

@@ -854,6 +855,7 @@ static struct irq_chip mpic_ipi_chip = {
 	.mask		= mpic_mask_ipi,
 	.unmask		= mpic_unmask_ipi,
 	.eoi		= mpic_end_ipi,
+	.end		= mpic_end_ipi,
 };
 #endif /* CONFIG_SMP */
 

@@ -864,6 +866,7 @@ static struct irq_chip mpic_irq_ht_chip = {
 	.mask		= mpic_mask_irq,
 	.unmask		= mpic_unmask_ht_irq,
 	.eoi		= mpic_end_ht_irq,
+	.end		= mpic_end_ht_irq,
 	.set_type	= mpic_set_irq_type,
 };
 #endif /* CONFIG_MPIC_U3_HT_IRQS */

index 55e6f39..8e743e0 100644
@@ -328,6 +328,9 @@ void qe_ic_cascade_low(unsigned int irq, struct irq_desc *desc)
 
 	if (cascade_irq != NO_IRQ)
 		generic_handle_irq(cascade_irq);
+
+	if (desc->chip->end)
+		desc->chip->end(irq);
 }
 
 void qe_ic_cascade_high(unsigned int irq, struct irq_desc *desc)

@@ -337,6 +340,9 @@ void qe_ic_cascade_high(unsigned int irq, struct irq_desc *desc)
 
 	if (cascade_irq != NO_IRQ)
 		generic_handle_irq(cascade_irq);
+
+	if (desc->chip->end)
+		desc->chip->end(irq);
 }
 
 void __init qe_ic_init(struct device_node *node, unsigned int flags)

1.5.0.6

I'm not familiar with the differences between IPIC and MPIC. What is this patch not needed for 83xx?

Timur Tabi
Linux Kernel Developer @ Freescale

Yup, this patch not needed for 83xx. IPIC doesn't have end()/eoi(). (..and MPIC doesn't have ack()).

Though...

Idially QEIC should do both ack() and end(), at the beginning and at the end of irq handling respectively.

I don't know (didn't look) why this works for 83xx w/o ack()... maybe IPIC don't need this. Or maybe there is a bug hiding.

Anton Vorontsov
email: [email protected]
backup email: [email protected]
irc://irc.freenode.net/bd2

Scott W told me that me that the IPIC doesn't have the concept of EOI ack. It just has IRQ masks.

Timur Tabi
Linux Kernel Developer @ Freescale

And the IRQ will be masked at the QEIC while being processed. Doing it this way allows another QE interrupt to come through while the first is being serviced.

It might make sense on MPIC to ack after masking at the QEIC, for this reason.

-Scott

That's true for IPIC, but MPIC has the concept of EOI ack - "An interrupt is considered in-service from the time its vector is read (through an IACK cycle) until the end of interrupt (EOI) register is written. generating what the PIC considers an EOI signal."

On MPC8568, QEIC is a interrupt source of MPIC, so it must send a EOI signal after the interrupt is served. otherwise, the QEIC interrupt is always in-service.

Haiying