Rework ASI instructions

Hi all,

The current implementation of ASI instructions on the SPARC target is correct for most cases on SPARC32, but is completely wrong on SPARC64.

The current implementation assumes that the ASI is encoded in the instruction, which is correct on SPARC32, but wrong on SPARC64 where the ASI register can be used if an immediate offset is specified the instructions instead. Moreover when the immediate ASI does not correspond to a normal memory access, the instructions are mapped to a load or a store. This does not work (and even on SPARC32) for instructions that loads and store at the same time (e.g. SWAPA, LDSTUBA).

The patch fixes that by defining ops for all those instructions, and calling helper_ld_asi() and helper_st_asi(). At the same times it fixes load instructions that are signed (e.g. LDSBA, LDSHA), and implements a few ASI on SPARC64: as if user primary, as if user primary LE, primary LE, primary no-fault LE.

Please note that the LDFA, LDDFA, STFA and STDFA instructions are still not correctly implemented, but this is not a regression.

With this patch I am able to boot a 64-bit Linux kernel on the sparc64-softmmu target up to the point where it queries OpenBIOS about the memory. This fails because OpenBIOS does not export the correct device.

Cheers,
Aurelien

Index: target-sparc/exec.h
===================================================================
RCS file: /sources/qemu/qemu/target-sparc/exec.h,v retrieving revision 1.19

diff -u -d -p -r1.19 exec.h
@@ -50,7 +50,7 @@ void cpu_unlock(void);
 void cpu_loop_exit(void);
 void helper_flush(target_ulong addr);
 void helper_ld_asi(int asi, int size, int sign);
-void helper_st_asi(int asi, int size, int sign);
+void helper_st_asi(int asi, int size);
 void helper_rett(void);
 void helper_ldfsr(void);
 void set_cwp(int new_cwp);

Index: target-sparc/op.c
===================================================================
RCS file: /sources/qemu/qemu/target-sparc/op.c,v
retrieving revision 1.39

Index: target-sparc/op_helper.c
===================================================================
RCS file: /sources/qemu/qemu/target-sparc/op_helper.c,v retrieving revision 1.36

Index: target-sparc/op_mem.h
===================================================================
RCS file: /sources/qemu/qemu/target-sparc/op_mem.h,v retrieving revision 1.9

diff -u -d -p -r1.9 op_mem.h
@@ -76,33 +76,6 @@ void OPPROTO glue(op_lddf, MEMSUFFIX) (v
 }
 
 #ifdef TARGET_SPARC64
-/* XXX: Should be Atomically */
-/* XXX: There are no cas[x] instructions, only cas[x]a */
-void OPPROTO glue(op_cas, MEMSUFFIX)(void)
-{
-    uint32_t tmp;
-
-    tmp = glue(ldl, MEMSUFFIX)(T0);
-    T2 &=  0xffffffffULL;
-    if (tmp == (T1 & 0xffffffffULL)) {
-        glue(stl, MEMSUFFIX)(T0, T2);
-    }
-    T2 = tmp;
-}
-
-void OPPROTO glue(op_casx, MEMSUFFIX)(void)
-{
-    uint64_t tmp;
-
-    // XXX
-    tmp = (uint64_t)glue(ldl, MEMSUFFIX)(T0) << 32;
-    tmp |= glue(ldl, MEMSUFFIX)(T0);
-    if (tmp == T1) {
-        glue(stq, MEMSUFFIX)(T0, T2);
-    }
-    T2 = tmp;
-}
-
 void OPPROTO glue(op_lduw, MEMSUFFIX)(void)
 {
     T1 = (uint64_t)(glue(ldl, MEMSUFFIX)(T0) & 0xffffffff);

Index: target-sparc/translate.c
===================================================================
RCS file: /sources/qemu/qemu/target-sparc/translate.c,v retrieving revision 1.68

  .''`.  Aurelien Jarno	            | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
 `. `'   [email protected]         | [email protected]
   `-    people.debian.org/~aurel32 | www.aurel32.net