CRIS toplevel
PATCH 1/1 CRIS toplevel
These patches add CRIS support to qemu top-level dir.
I had to increase the size of the packet buffer for gdb, I could try to find a size less than 4k if it's a problem.
Signature · 11 lines
Edgar E. Iglesias Axis Communications AB cpu-exec.c | 62 +++++++++++++++++++++++++++++++++++++++++++++++++- exec-all.h | 2 + exec.c | 4 +++ gdbstub.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++++++++- softmmu_header.h | 6 +++++ vl.c | 2 + vl.h | 3 ++ 7 files changed, 143 insertions(+), 2 deletions(-)
cpu-exec.c +61 -1
@@ -210,6 +210,10 @@ static inline TranslationBlock *tb_find_fast(void) flags = env->ps; cs_base =0 ; pc = env->pc; +#elif defined(TARGET_CRIS ) + flags =0 ; + cs_base =0 ; + pc = env->pc;#else #error unsupported CPU#endif
@@ -284,6 +288,7 @@ int cpu_exec(CPUState *env1)#elif defined(TARGET_PPC )#elif defined(TARGET_MIPS )#elif defined(TARGET_SH4 ) +#elif defined(TARGET_CRIS )/* XXXXX */ #else #error unsupported target CPU
@@ -335,6 +340,8 @@ int cpu_exec(CPUState *env1)do_interrupt (env);#elif defined(TARGET_ALPHA )do_interrupt (env); +#elif defined(TARGET_CRIS ) +do_interrupt (env);#elif defined(TARGET_M68K )do_interrupt (0 );#endif
@@ -385,7 +392,7 @@ int cpu_exec(CPUState *env1)cpu_loop_exit (); }#if defined(TARGET_ARM ) || defined(TARGET_SPARC ) || defined(TARGET_MIPS ) || \ - defined(TARGET_PPC ) || defined(TARGET_ALPHA ) + defined(TARGET_PPC ) || defined(TARGET_ALPHA ) || defined(TARGET_CRIS )if (interrupt_request &CPU_INTERRUPT_HALT ) { env->interrupt_request &= ~CPU_INTERRUPT_HALT ; env->halted =1 ;
@@ -517,6 +524,11 @@ int cpu_exec(CPUState *env1)if (interrupt_request &CPU_INTERRUPT_HARD ) {do_interrupt (env); } +#elif defined(TARGET_CRIS ) +if (interrupt_request &CPU_INTERRUPT_HARD ) { +do_interrupt (env); + env->interrupt_request &= ~CPU_INTERRUPT_HARD ; + }#elif defined(TARGET_M68K )if (interrupt_request &CPU_INTERRUPT_HARD && ((env->sr & SR_I) >> SR_I_SHIFT)
@@ -576,6 +588,8 @@ int cpu_exec(CPUState *env1)cpu_dump_state (env, logfile, fprintf,0 );#elif defined(TARGET_ALPHA )cpu_dump_state (env, logfile, fprintf,0 ); +#elif defined(TARGET_CRIS ) +cpu_dump_state (env, logfile, fprintf,0 );#else #error unsupported target CPU#endif
@@ -769,6 +783,7 @@ int cpu_exec(CPUState *env1)#elif defined(TARGET_MIPS )#elif defined(TARGET_SH4 )#elif defined(TARGET_ALPHA ) +#elif defined(TARGET_CRIS )/* XXXXX */ #else #error unsupported target CPU
@@ -1200,6 +1215,51 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address,/* never comes here */ return 1 ; } +#elif defined (TARGET_CRIS ) +static inline int handle_cpu_signal (unsigned long pc,unsigned long address, +int is_write,sigset_t *old_set, +void *puc) +{ +TranslationBlock *tb; +int ret; + +if (cpu_single_env) + env = cpu_single_env;/* XXX: find a correct solution for multithread */ +#if defined(DEBUG_SIGNAL ) +printf ("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n" , + pc, address, is_write, *(unsigned long *)old_set); +#endif +/* XXX: locking issue */ +if (is_write &&page_unprotect (h2g (address), pc, puc)) { +return 1 ; + } + +/* see if it is an MMU fault */ + ret =cpu_cris_handle_mmu_fault (env, address, is_write,1 ,0 ); +if (ret <0 ) +return 0 ;/* not an MMU fault */ +if (ret ==0 ) +return 1 ;/* the MMU fault was handled without causing real CPU fault */ + +/* now we have a real cpu fault */ + tb =tb_find_pc (pc); +if (tb) { +/* the PC is inside the translated code. It means that we have +a virtual CPU fault */ +cpu_restore_state (tb, env, pc, puc); + } +#if 0 +printf ("PF exception: NIP=0x%08x error=0x%x %p\n" , + env->nip, env->error_code, tb); +#endif +/* we restore the process signal mask as the sigreturn should +do it (XXX: use sigsetjmp) */ +sigprocmask (SIG_SETMASK , old_set,NULL ); +cpu_loop_exit (); +/* never comes here */ +return 1 ; +} +#else #error unsupported target CPU#endif
exec-all.h +2 -0
@@ -617,6 +617,8 @@ static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) is_user = ((env->ps >>3 ) &3 );#elif defined (TARGET_M68K ) is_user = ((env->sr &SR_S ) ==0 ); +#elif defined (TARGET_CRIS ) + is_user = (0 );#else #error unimplemented CPU#endif
exec.c +4 -0
@@ -2066,6 +2066,8 @@ static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr)#endif #ifdef TARGET_SPARC do_unassigned_access (addr,0 ,0 ,0 ); +#elif TARGET_CRIS +do_unassigned_access (addr,0 ,0 ,0 );#endif return 0 ; }
@@ -2077,6 +2079,8 @@ static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_#endif #ifdef TARGET_SPARC do_unassigned_access (addr,1 ,0 ,0 ); +#elif TARGET_CRIS +do_unassigned_access (addr,1 ,0 ,0 );#endif }
gdbstub.c +65 -1
90 lines not on this page · raw message
softmmu_header.h +6 -0
@@ -67,6 +67,9 @@#define CPU_MEM_INDEX ((env->ps >> 3) & 3)#elif defined (TARGET_M68K )#define CPU_MEM_INDEX ((env->sr & SR_S) == 0) +#elif defined (TARGET_CRIS ) +/* CRIS FIXME: I guess we want to validate supervisor mode acceses here. */ +#define CPU_MEM_INDEX (0)#else #error unsupported CPU#endif
@@ -90,6 +93,9 @@#define CPU_MEM_INDEX ((env->ps >> 3) & 3)#elif defined (TARGET_M68K )#define CPU_MEM_INDEX ((env->sr & SR_S) == 0) +#elif defined (TARGET_CRIS ) +/* CRIS FIXME: I guess we want to validate supervisor mode acceses here. */ +#define CPU_MEM_INDEX (0)#else #error unsupported CPU#endif
vl.c +2 -0
@@ -7389,6 +7389,8 @@ void register_machines(void)#elif defined(TARGET_M68K )qemu_register_machine (&mcf5208evb_machine);qemu_register_machine (&an5206_machine); +#elif defined(TARGET_CRIS ) +qemu_register_machine (&bareetraxfs_machine);#else #error unsupported CPU#endif
vl.h +3 -0
@@ -1172,6 +1172,9 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);void piix4_smbus_register_device (SMBusDevice *dev,uint8_t addr);void acpi_bios_init (void ); +/* Axis ETRAX. */ +extern QEMUMachine bareetraxfs_machine; +/* pc.c */ extern QEMUMachine pc_machine;extern QEMUMachine isapc_machine;