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ppc4xx: Fix incorrect 33/66MHz PCI clock log-message on Sequoia & Yosemite

PATCH New Stefan Roese 1 participant 1 message Oct 15, 2007

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Stefan Roese

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PATCH 1/1 ppc4xx: Fix incorrect 33/66MHz PCI clock log-message on Sequoia & Yosemite

The BCSR status bit for the 66MHz PCI operation was correctly addressed (MSB/LSB problem). Now the correct currently setup PCI frequency is displayed upon bootup.

This patch also fixes this problem on Rainier & Yellowstone, since these boards use the same souce code as Sequoia & Yosemite do.

Signed-off-by Stefan Roese <[email protected]>
---
 board/amcc/sequoia/sequoia.c   |    7 ++++---
 board/amcc/yosemite/yosemite.c |    7 +++++--
 include/configs/sequoia.h      |    2 ++
 include/configs/yosemite.h     |    2 ++
 4 files changed, 13 insertions(+), 5 deletions(-)
board/amcc/sequoia/sequoia.c +4 -3
index f823117..4e47ab3 100644
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2006
+ * (C) Copyright 2006-2007
  * Stefan Roese, DENX Software Engineering, sr at denx.de.
  *
  * (C) Copyright 2006

@@ -24,6 +24,7 @@
 
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 #include <ppc440.h>
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -362,8 +363,8 @@ int checkboard(void)
 	printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
 #endif
 
-	rev = in8(CFG_BCSR_BASE + 0);
-	val = in8(CFG_BCSR_BASE + 5) & 0x01;
+	rev = in_8((void *)(CFG_BCSR_BASE + 0));
+	val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
 	printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
 
 	if (s != NULL) {
board/amcc/yosemite/yosemite.c +5 -2
index 912f09e..6ec922a 100644
@@ -1,4 +1,6 @@
 /*
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr at denx.de.
  *
  * See file CREDITS for list of people who contributed to this
  * project.

@@ -22,6 +24,7 @@
 #include <common.h>
 #include <ppc4xx.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 #include <spd_sdram.h>
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -181,8 +184,8 @@ int checkboard(void)
 	printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
 #endif
 
-	rev = *(u8 *)(CFG_CPLD + 0);
-	val = *(u8 *)(CFG_CPLD + 5) & 0x01;
+	rev = in_8((void *)(CFG_BCSR_BASE + 0));
+	val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
 	printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
 
 	if (s != NULL) {
include/configs/sequoia.h +2 -0
index c2e1386..600f98c 100644
@@ -450,6 +450,8 @@
 #define CFG_EBC_PB2AP		0x24814580
 #define CFG_EBC_PB2CR		(CFG_BCSR_BASE | 0x38000)
 
+#define CFG_BCSR5_PCI66EN	0x80
+
 /*-----------------------------------------------------------------------
  * NAND FLASH
  *----------------------------------------------------------------------*/
include/configs/yosemite.h +2 -0
index 6a5b7f1..35bce4a 100644
@@ -359,6 +359,8 @@
 #define CFG_EBC_PB2AP		0x04814500
 #define CFG_EBC_PB2CR		(CFG_CPLD | 0x18000)
 
+#define CFG_BCSR5_PCI66EN	0x80
+
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
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