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tg3: Prescaler fix

PATCH Applied Matt Carlson 2 participants 2 messages Nov 10, 2007 – Nov 13, 2007

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Networking Network drivers
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Matt Carlson

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#0 lore raw

PATCH 9/13 tg3: Prescaler fix

Internal hardware timers become inaccurate after link events. Clock frequency switches performed by the CPMU fail to adjust timer prescalers. The fix is to detect core clock frequency changes during link events and adjust the timer prescalers accordingly.

Signed-off-by Matt Carlson <[email protected]>
Signed-off-by Michael Chan <[email protected]>
drivers/net/tg3.c +16 -0
index bb3b734..ecd64a2 100644
@@ -3154,6 +3154,22 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
 		err = tg3_setup_copper_phy(tp, force_reset);
 	}
 
+	if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0) {
+		u32 val, scale;
+
+		val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
+		if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
+			scale = 65;
+		else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
+			scale = 6;
+		else
+			scale = 12;
+
+		val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
+		val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
+		tw32(GRC_MISC_CFG, val);
+	}
+
 	if (tp->link_config.active_speed == SPEED_1000 &&
 	    tp->link_config.active_duplex == DUPLEX_HALF)
 		tw32(MAC_TX_LENGTHS,
drivers/net/tg3.h +8 -1
index 5b799ff..d325ab5 100644
@@ -874,7 +874,14 @@
 #define TG3_CPMU_HST_ACC		0x0000361c
 #define  CPMU_HST_ACC_MACCLK_MASK	 0x001f0000
 #define  CPMU_HST_ACC_MACCLK_6_25	 0x00130000
-/* 0x3620 --> 0x365c unused */
+/* 0x3620 --> 0x3630 unused */
+
+#define TG3_CPMU_CLCK_STAT		0x00003630
+#define  CPMU_CLCK_STAT_MAC_CLCK_MASK	 0x001f0000
+#define  CPMU_CLCK_STAT_MAC_CLCK_62_5	 0x00000000
+#define  CPMU_CLCK_STAT_MAC_CLCK_12_5	 0x00110000
+#define  CPMU_CLCK_STAT_MAC_CLCK_6_25	 0x00130000
+/* 0x3634 --> 0x365c unused */
 
 #define TG3_CPMU_MUTEX_REQ		0x0000365c
 #define  CPMU_MUTEX_REQ_DRIVER		 0x00001000
maintainer
#1 lore raw

From: "Matt Carlson" <[email protected]>
Date: Fri, 09 Nov 2007 16:38:59 -0800

Quoted 7 lines

Internal hardware timers become inaccurate after link events. Clock frequency switches performed by the CPMU fail to adjust timer prescalers. The fix is to detect core clock frequency changes during link events and adjust the timer prescalers accordingly.

Signed-off-by Matt Carlson <[email protected]>
Signed-off-by Michael Chan <[email protected]>

This CPMU seems very sensitive in it's MAC/PHY interactions. :-)

Patch applied, thanks!