LinkStation / KuroBox from Buffalo support

index b0bf733..198d074 100644
@@ -226,6 +226,8 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
 
 #define AMD_ID_LV320B_2 0x221A221A	/* 2d ID word for AM29LV320MB at 0x38 */
 #define AMD_ID_LV320B_3 0x22002200	/* 3d ID word for AM29LV320MB at 0x3c */
+#define AMD_ID_LV320T_2 0x221A221A	/* 2d ID word for AM29LV320MT at 0x38 */
+#define AMD_ID_LV320T_3 0x22012201	/* 3d ID word for AM29LV320MT at 0x3c */
 
 #define AMD_ID_LV640U	0x22D722D7	/* 29LV640U ID (64 M, uniform sectors)	*/
 #define AMD_ID_LV650U	0x22D722D7	/* 29LV650U ID (64 M, uniform sectors)	*/

@@ -259,6 +261,8 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
 #define STM_ID_29W320DB 0x22CB22CB	/* M29W320DB ID (32 M, bottom boot sect)	*/
 #define STM_ID_29W320ET 0x22562256	/* M29W320ET ID (32 M, top boot sector) */
 #define STM_ID_29W320EB 0x22572257	/* M29W320EB ID (32 M, bottom boot sect)*/
+#define STM_ID_29W324DT 0x225C225C	/* M29W324DT ID (32 M, top boot sector) */
+#define STM_ID_29W324DB 0x225D225D	/* M29W324DB ID (32 M, bottom boot sect)*/
 #define STM_ID_29W040B	0x00E300E3	/* M29W040B ID (4M = 512K x 8)	*/
 #define FLASH_PSD4256GV 0x00E9		/* PSD4256 Flash and CPLD combination	*/
 

@@ -367,6 +371,8 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
 #define FLASH_STM800AB	0x0051		/* STM M29WF800AB  (  8M = 512K x 16 )	*/
 #define FLASH_STMW320DT 0x0052		/* STM M29W320DT   (32 M, top boot sector)	*/
 #define FLASH_STMW320DB 0x0053		/* STM M29W320DB   (32 M, bottom boot sect)*/
+#define FLASH_STMW324DT 0x005C		/* STM M29W324DT   (32 M, top boot sector)	*/
+#define FLASH_STMW324DB 0x005D		/* STM M29W324DB   (32 M, bottom boot sect)*/
 #define FLASH_STM320DB	0x00CB		/* STM M29W320DB (4M = 64K x 64, bottom)*/
 #define FLASH_STM800DT	0x00D7		/* STM M29W800DT (1M = 64K x 16, top)	*/
 #define FLASH_STM800DB	0x005B		/* STM M29W800DB (1M = 64K x 16, bottom)*/

index 63ea2cc..1d7f31c 100644
@@ -48,7 +48,10 @@
 *
 *    Indent Options: indent -kr -i8
 ***************************************************************************/
-
+/*
+ * 26 August 2006 Mihai Georgian <[email protected]>
+ * Modified to use le32_to_cpu and cpu_to_le32 properly
+ */
 #include <common.h>
 #include <malloc.h>
 #include <net.h>

@@ -68,12 +71,7 @@
 static u32 ioaddr;
 
 /* Condensed operations for readability. */
-#define virt_to_le32desc(addr)	cpu_to_le32(virt_to_bus(addr))
-#define le32desc_to_virt(addr)	bus_to_virt(le32_to_cpu(addr))
-
 #define currticks()	get_timer(0)
-#define bus_to_phys(a)	pci_mem_to_phys((pci_dev_t)dev->priv, a)
-#define phys_to_bus(a)	pci_phys_to_mem((pci_dev_t)dev->priv, a)
 
 /* media options */
 #define MAX_UNITS 8

@@ -102,7 +100,7 @@ static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
 #define RTL_MIN_IO_SIZE 0x80
 #define TX_TIMEOUT  (6*HZ)
 
-/* write/read MMIO register */
+/* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
 #define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))
 #define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))
 #define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))

@@ -218,7 +216,7 @@ enum RTL8169_register_content {
 	PHY_Enable_Auto_Nego = 0x1000,
 
 	/* PHY_STAT_REG = 1; */
-	PHY_Auto_Neco_Comp = 0x0020,
+	PHY_Auto_Nego_Comp = 0x0020,
 
 	/* PHY_AUTO_NEGO_REG = 4; */
 	PHY_Cap_10_Half = 0x0020,

@@ -413,23 +411,23 @@ static int rtl_recv(struct eth_device *dev)
 	ioaddr = dev->iobase;
 
 	cur_rx = tpc->cur_rx;
-	if ((tpc->RxDescArray[cur_rx].status & OWNbit) == 0) {
-		if (!(tpc->RxDescArray[cur_rx].status & RxRES)) {
+	if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
+		if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
 			unsigned char rxdata[RX_BUF_LEN];
-			length = (int) (tpc->RxDescArray[cur_rx].
-						status & 0x00001FFF) - 4;
+			length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
+						status) & 0x00001FFF) - 4;
 
 			memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
 			NetReceive(rxdata, length);
 
 			if (cur_rx == NUM_RX_DESC - 1)
 				tpc->RxDescArray[cur_rx].status =
-				    (OWNbit | EORbit) + RX_BUF_SIZE;
+					cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
 			else
 				tpc->RxDescArray[cur_rx].status =
-				    OWNbit + RX_BUF_SIZE;
+					cpu_to_le32(OWNbit + RX_BUF_SIZE);
 			tpc->RxDescArray[cur_rx].buf_addr =
-			    virt_to_bus(tpc->RxBufferRing[cur_rx]);
+				cpu_to_le32(tpc->RxBufferRing[cur_rx]);
 		} else {
 			puts("Error Rx");
 		}

@@ -454,6 +452,7 @@ static int rtl_send(struct eth_device *dev, volatile void *packet, int length)
 	u8 *ptxb;
 	int entry = tpc->cur_tx % NUM_TX_DESC;
 	u32 len = length;
+	int ret;
 
 #ifdef DEBUG_RTL8169_TX
 	int stime = currticks();

@@ -470,34 +469,38 @@ static int rtl_send(struct eth_device *dev, volatile void *packet, int length)
 	while (len < ETH_ZLEN)
 		ptxb[len++] = '\0';
 
-	tpc->TxDescArray[entry].buf_addr = virt_to_bus(ptxb);
+	tpc->TxDescArray[entry].buf_addr = cpu_to_le32(ptxb);
 	if (entry != (NUM_TX_DESC - 1)) {
 		tpc->TxDescArray[entry].status =
-		    (OWNbit | FSbit | LSbit) | ((len > ETH_ZLEN) ?
-						len : ETH_ZLEN);
+			cpu_to_le32((OWNbit | FSbit | LSbit) |
+				    ((len > ETH_ZLEN) ? len : ETH_ZLEN));
 	} else {
 		tpc->TxDescArray[entry].status =
-		    (OWNbit | EORbit | FSbit | LSbit) |
-		    ((len > ETH_ZLEN) ? length : ETH_ZLEN);
+			cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
+				    ((len > ETH_ZLEN) ? len : ETH_ZLEN));
 	}
 	RTL_W8(TxPoll, 0x40);	/* set polling bit */
 
 	tpc->cur_tx++;
 	to = currticks() + TX_TIMEOUT;
-	while ((tpc->TxDescArray[entry].status & OWNbit) && (currticks() < to));	/* wait */
+	while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
+				&& (currticks() < to));	/* wait */
 
 	if (currticks() >= to) {
 #ifdef DEBUG_RTL8169_TX
 		puts ("tx timeout/error\n");
 		printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
 #endif
-		return 0;
+		ret = 0;
 	} else {
 #ifdef DEBUG_RTL8169_TX
 		puts("tx done\n");
 #endif
-		return length;
+		ret = length;
 	}
+	/* Delay to make net console (nc) work properly */
+	udelay(20);
+	return ret;
 }
 
 static void rtl8169_set_rx_mode(struct eth_device *dev)

@@ -564,8 +567,8 @@ static void rtl8169_hw_start(struct eth_device *dev)
 
 	tpc->cur_rx = 0;
 
-	RTL_W32(TxDescStartAddr, virt_to_le32desc(tpc->TxDescArray));
-	RTL_W32(RxDescStartAddr, virt_to_le32desc(tpc->RxDescArray));
+	RTL_W32(TxDescStartAddr, tpc->TxDescArray);
+	RTL_W32(RxDescStartAddr, tpc->RxDescArray);
 	RTL_W8(Cfg9346, Cfg9346_Lock);
 	udelay(10);
 

@@ -603,13 +606,14 @@ static void rtl8169_init_ring(struct eth_device *dev)
 	for (i = 0; i < NUM_RX_DESC; i++) {
 		if (i == (NUM_RX_DESC - 1))
 			tpc->RxDescArray[i].status =
-			    (OWNbit | EORbit) + RX_BUF_SIZE;
+				cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
 		else
-			tpc->RxDescArray[i].status = OWNbit + RX_BUF_SIZE;
+			tpc->RxDescArray[i].status =
+				cpu_to_le32(OWNbit + RX_BUF_SIZE);
 
 		tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
 		tpc->RxDescArray[i].buf_addr =
-		    virt_to_bus(tpc->RxBufferRing[i]);
+			cpu_to_le32(tpc->RxBufferRing[i]);
 	}
 
 #ifdef DEBUG_RTL8169

@@ -623,8 +627,6 @@ RESET - Finish setting up the ethernet interface
 static void rtl_reset(struct eth_device *dev, bd_t *bis)
 {
 	int i;
-	u8 diff;
-	u32 TxPhyAddr, RxPhyAddr;
 
 #ifdef DEBUG_RTL8169
 	int stime = currticks();

@@ -632,25 +634,14 @@ static void rtl_reset(struct eth_device *dev, bd_t *bis)
 #endif
 
 	tpc->TxDescArrays = tx_ring;
-	if (tpc->TxDescArrays == 0)
-		puts("Allot Error");
 	/* Tx Desscriptor needs 256 bytes alignment; */
-	TxPhyAddr = virt_to_bus(tpc->TxDescArrays);
-	diff = 256 - (TxPhyAddr - ((TxPhyAddr >> 8) << 8));
-	TxPhyAddr += diff;
-	tpc->TxDescArray = (struct TxDesc *) (tpc->TxDescArrays + diff);
+	tpc->TxDescArray = (struct TxDesc *) ((unsigned long)(tpc->TxDescArrays +
+							      255) & ~255);
 
 	tpc->RxDescArrays = rx_ring;
 	/* Rx Desscriptor needs 256 bytes alignment; */
-	RxPhyAddr = virt_to_bus(tpc->RxDescArrays);
-	diff = 256 - (RxPhyAddr - ((RxPhyAddr >> 8) << 8));
-	RxPhyAddr += diff;
-	tpc->RxDescArray = (struct RxDesc *) (tpc->RxDescArrays + diff);
-
-	if (tpc->TxDescArrays == NULL || tpc->RxDescArrays == NULL) {
-		puts("Allocate RxDescArray or TxDescArray failed\n");
-		return;
-	}
+	tpc->RxDescArray = (struct RxDesc *) ((unsigned long)(tpc->RxDescArrays +
+							      255) & ~255);
 
 	rtl8169_init_ring(dev);
 	rtl8169_hw_start(dev);

@@ -733,7 +724,7 @@ static int rtl_init(struct eth_device *dev, bd_t *bis)
 
 	/* Get MAC address.  FIXME: read EEPROM */
 	for (i = 0; i < MAC_ADDR_LEN; i++)
-		dev->enetaddr[i] = RTL_R8(MAC0 + i);
+		bis->bi_enetaddr[i] = dev->enetaddr[i] = RTL_R8(MAC0 + i);
 
 #ifdef DEBUG_RTL8169
 	printf("MAC Address");

@@ -808,7 +799,7 @@ static int rtl_init(struct eth_device *dev, bd_t *bis)
 		/* wait for auto-negotiation process */
 		for (i = 10000; i > 0; i--) {
 			/* check if auto-negotiation complete */
-			if (mdio_read(PHY_STAT_REG) & PHY_Auto_Neco_Comp) {
+			if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) {
 				udelay(100);
 				option = RTL_R8(PHYstatus);
 				if (option & _1000bpsF) {

@@ -818,13 +809,12 @@ static int rtl_init(struct eth_device *dev, bd_t *bis)
 #endif
 				} else {
 #ifdef DEBUG_RTL8169
-					printf
-					    ("%s: %sMbps %s-duplex operation.\n",
-					     dev->name,
-					     (option & _100bps) ? "100" :
-					     "10",
-					     (option & FullDup) ? "Full" :
-					     "Half");
+					printf("%s: %sMbps %s-duplex operation.\n",
+					       dev->name,
+					       (option & _100bps) ? "100" :
+					       "10",
+					       (option & FullDup) ? "Full" :
+					       "Half");
 #endif
 				}
 				break;

@@ -869,7 +859,7 @@ int rtl8169_initialize(bd_t *bis)
 		sprintf (dev->name, "RTL8169#%d", card_number);
 
 		dev->priv = (void *) devno;
-		dev->iobase = (int)bus_to_phys(iobase);
+		dev->iobase = (int)pci_mem_to_phys(devno, iobase);
 
 		dev->init = rtl_reset;
 		dev->halt = rtl_halt;

index 3b10452..638d3d8 100644
@@ -1472,6 +1472,8 @@
 #define PCI_DEVICE_ID_ITE_IT8172G	0x8172
 #define PCI_DEVICE_ID_ITE_IT8172G_AUDIO 0x0801
 #define PCI_DEVICE_ID_ITE_IT8181	0x8181
+#define PCI_DEVICE_ID_ITE_8211		0x8211
+#define PCI_DEVICE_ID_ITE_8212		0x8212
 #define PCI_DEVICE_ID_ITE_8872		0x8872
 
 #define PCI_DEVICE_ID_ITE_IT8330G_0	0xe886

@@ -2050,3 +2052,6 @@
 #define PCI_DEVICE_ID_MICROGATE_USC	0x0010
 #define PCI_DEVICE_ID_MICROGATE_SCC	0x0020
 #define PCI_DEVICE_ID_MICROGATE_SCA	0x0030
+
+#define PCI_VENDOR_ID_ADMTEK 0x1317
+#define PCI_DEVICE_ID_ADMTEK_AN983B 0x985

index d5275dc..39ba49b 100644
@@ -47,6 +47,7 @@
  */
 #define DE4X5_BMR	0x000		/* Bus Mode Register */
 #define DE4X5_TPD	0x008		/* Transmit Poll Demand Reg */
+#define DE4X5_RPD	0x010		/* Receive Poll Demand Reg */
 #define DE4X5_RRBA	0x018		/* RX Ring Base Address Reg */
 #define DE4X5_TRBA	0x020		/* TX Ring Base Address Reg */
 #define DE4X5_STS	0x028		/* Status Register */

@@ -64,6 +65,7 @@
 #define OMR_PS		0x00040000	/* Port Select */
 #define OMR_SDP		0x02000000	/* SD Polarity - MUST BE ASSERTED */
 #define OMR_PM		0x00000080	/* Pass All Multicast */
+#define OMR_PMS		0x00000040	/* Promiscuous */
 
 /* Descriptor bits.
  */

@@ -97,6 +99,29 @@
 
 #define POLL_DEMAND	1
 
+/* The chip types have been taken from linux-2.4.31
+ * drivers/net/tulip/tulip.h
+ * Only COMET is used for now
+ */
+enum chips {
+	DC21040 = 0,
+	DC21041 = 1,
+	DC21140 = 2,
+	DC21142 = 3, DC21143 = 3,
+	LC82C168,
+	MX98713,
+	MX98715,
+	MX98725,
+	AX88140,
+	PNIC2,
+	COMET,
+	COMPEX9881,
+	I21145,
+	DM910X,
+	CONEXANT,
+};
+static int chip_idx = DC21143;
+
 #ifdef CONFIG_TULIP_FIX_DAVICOM
 #define RESET_DM9102(dev) {\
     unsigned long i;\

@@ -108,26 +133,23 @@
 #else
 #define RESET_DE4X5(dev) {\
     int i;\
-    i=INL(dev, DE4X5_BMR);\
-    udelay(1000);\
+    i=0x01A04000;\
     OUTL(dev, i | BMR_SWR, DE4X5_BMR);\
     udelay(1000);\
     OUTL(dev, i, DE4X5_BMR);\
     udelay(1000);\
-    for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\
-    udelay(1000);\
 }
 #endif
 
 #define START_DE4X5(dev) {\
-    s32 omr; \
+    u32 omr; \
     omr = INL(dev, DE4X5_OMR);\
     omr |= OMR_ST | OMR_SR;\
     OUTL(dev, omr, DE4X5_OMR);		/* Enable the TX and/or RX */\
 }
 
 #define STOP_DE4X5(dev) {\
-    s32 omr; \
+    u32 omr; \
     omr = INL(dev, DE4X5_OMR);\
     omr &= ~(OMR_ST|OMR_SR);\
     OUTL(dev, omr, DE4X5_OMR);		/* Disable the TX and/or RX */ \

@@ -135,31 +157,39 @@
 
 #define NUM_RX_DESC PKTBUFSRX
 #ifndef CONFIG_TULIP_FIX_DAVICOM
-	#define NUM_TX_DESC 1			/* Number of TX descriptors   */
+	#define NUM_TX_DESC 2		/* Number of TX descriptors   */
 #else
 	#define NUM_TX_DESC 4
 #endif
-#define RX_BUFF_SZ  PKTSIZE_ALIGN
+#define BUFLEN  1536
 
 #define TOUT_LOOP   1000000
 
 #define SETUP_FRAME_LEN 192
 #define ETH_ALEN	6
+#define ETH_ZLEN	60
 
 struct de4x5_desc {
-	volatile s32 status;
+	volatile u32 status;
 	u32 des1;
 	u32 buf;
 	u32 next;
 };
 
-static struct de4x5_desc rx_ring[NUM_RX_DESC] __attribute__ ((aligned(32))); /* RX descriptor ring         */
-static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring         */
-static int rx_new;                             /* RX descriptor ring pointer */
-static int tx_new;                             /* TX descriptor ring pointer */
+/* Note: transmit and receive buffers must be longword aligned and
+   longword divisable */
+
+/* TX descriptor ring */
+static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(4)));
+/* TX buffer */
+static unsigned char txb[BUFLEN] __attribute__ ((aligned(32)));
+
+/* RX descriptor ring */
+static struct de4x5_desc rx_ring[NUM_RX_DESC] __attribute__ ((aligned(4)));
+/* RX buffers */
+static unsigned char rxb[NUM_RX_DESC * BUFLEN] __attribute__ ((aligned(32)));
 
-static char rxRingSize;
-static char txRingSize;
+static int rx_new;		/* RX descriptor ring pointer */
 
 #if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
 static void  sendto_srom(struct eth_device* dev, u_int command, u_long addr);

@@ -204,6 +234,7 @@ static void OUTL(struct eth_device* dev, int command, u_long addr)
 static struct pci_device_id supported[] = {
 	{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
 	{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
+	{ PCI_VENDOR_ID_ADMTEK, PCI_DEVICE_ID_ADMTEK_AN983B },
 #ifdef CONFIG_TULIP_FIX_DAVICOM
 	{ PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DAVICOM_DM9102A },
 #endif

@@ -214,29 +245,41 @@ int dc21x4x_initialize(bd_t *bis)
 {
 	int             	idx=0;
 	int             	card_number = 0;
-	unsigned int           	cfrv;
+	unsigned int		cfrv;
 	unsigned char   	timer;
 	pci_dev_t		devbusfn;
 	unsigned int		iobase;
 	unsigned short		status;
 	struct eth_device* 	dev;
+	u16			vendor;
+	u16			device;
 
 	while(1) {
 		devbusfn =  pci_find_devices(supported, idx++);
 		if (devbusfn == -1) {
 			break;
 		}
+		pci_read_config_word(devbusfn, PCI_VENDOR_ID, &vendor);
+		pci_read_config_word(devbusfn, PCI_DEVICE_ID, &device);
 
-		/* Get the chip configuration revision register. */
-		pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);
+		debug("dc21x4x: devbusfn: %08lX, VID: %08lX, DID: %08lX\n",
+			devbusfn, vendor, device);
+
+		if (vendor == PCI_VENDOR_ID_ADMTEK && \
+		    device == PCI_DEVICE_ID_ADMTEK_AN983B) {
+			chip_idx = COMET;
+		} else {
+			/* Get the chip configuration revision register. */
+			pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);
 
 #ifndef CONFIG_TULIP_FIX_DAVICOM
-		if ((cfrv & CFRV_RN) < DC2114x_BRK ) {
-			printf("Error: The chip is not DC21143.\n");
-			continue;
-		}
+			if ((cfrv & CFRV_RN) < DC2114x_BRK ) {
+				printf("Error: The chip is not DC21143.\n");
+				idx++;
+				continue;
+			}
 #endif
-
+		}
 		pci_read_config_word(devbusfn, PCI_COMMAND, &status);
 		status |=
 #ifdef CONFIG_TULIP_USE_IO

@@ -286,7 +329,10 @@ int dc21x4x_initialize(bd_t *bis)
 #ifdef CONFIG_TULIP_FIX_DAVICOM
 		sprintf(dev->name, "Davicom#%d", card_number);
 #else
-		sprintf(dev->name, "dc21x4x#%d", card_number);
+		if (chip_idx == COMET)
+			sprintf(dev->name, "COMET#%d", card_number);
+		else
+			sprintf(dev->name, "dc21x4x#%d", card_number);
 #endif
 
 #ifdef CONFIG_TULIP_USE_IO

@@ -303,8 +349,6 @@ int dc21x4x_initialize(bd_t *bis)
 		/* Ensure we're not sleeping. */
 		pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
 
-		udelay(10 * 1000);
-
 #ifndef CONFIG_TULIP_FIX_DAVICOM
 		read_hw_addr(dev, bis);
 #endif

@@ -321,8 +365,9 @@ static int dc21x4x_init(struct eth_device* dev, bd_t* bis)
 	int		i;
 	int		devbusfn = (int) dev->priv;
 
-	/* Ensure we're not sleeping. */
-	pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
+#if defined(DEBUG_TULIP) || defined(DEBUG_TRACE)
+	serial_printf("%0lu %s\n", get_timer(0), __FUNCTION__);
+#endif
 
 #ifdef CONFIG_TULIP_FIX_DAVICOM
 	RESET_DM9102(dev);

@@ -330,57 +375,71 @@ static int dc21x4x_init(struct eth_device* dev, bd_t* bis)
 	RESET_DE4X5(dev);
 #endif
 
-	if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
-		printf("Error: Cannot reset ethernet controller.\n");
-		return 0;
-	}
-
 #ifdef CONFIG_TULIP_SELECT_MEDIA
 	dc21x4x_select_media(dev);
 #else
-	OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
+	if (chip_idx == COMET) {
+		/* No multicast */
+		OUTL(dev, 0, 0xAC);
+		OUTL(dev, 0, 0xB0);
+	} else {
+		OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
+	}
 #endif
 
 	for (i = 0; i < NUM_RX_DESC; i++) {
 		rx_ring[i].status = cpu_to_le32(R_OWN);
-		rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
-		rx_ring[i].buf = cpu_to_le32(phys_to_bus((u32) NetRxPackets[i]));
-#ifdef CONFIG_TULIP_FIX_DAVICOM
-		rx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &rx_ring[(i+1) % NUM_RX_DESC]));
-#else
-		rx_ring[i].next = 0;
-#endif
+		rx_ring[i].des1 = cpu_to_le32(BUFLEN);
+		rx_ring[i].buf = cpu_to_le32(phys_to_bus((u32)&rxb[i * BUFLEN]));
+		rx_ring[i].next = cpu_to_le32(phys_to_bus((u32)&rx_ring[i+1]));
 	}
+	/* Write the end of list marker to the descriptor lists. */
+	rx_ring[NUM_RX_DESC - 1].des1 |= cpu_to_le32(RD_RER);
+	rx_ring[NUM_RX_DESC - 1].next = cpu_to_le32(phys_to_bus((u32)&rx_ring[0]));
 
-	for (i=0; i < NUM_TX_DESC; i++) {
-		tx_ring[i].status = 0;
-		tx_ring[i].des1 = 0;
-		tx_ring[i].buf = 0;
+	/* Point to the first descriptor */
+	rx_new = 0;
 
-#ifdef CONFIG_TULIP_FIX_DAVICOM
-	tx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &tx_ring[(i+1) % NUM_TX_DESC]));
-#else
-		tx_ring[i].next = 0;
-#endif
-	}
+	/* We only use 1 transmit buffer, but we use 2 descriptors so
+	   transmit engines have somewhere to point to if they feel the need */
+
+	tx_ring[0].status = 0;
+	tx_ring[0].des1 = 0;
+	tx_ring[0].buf = cpu_to_le32(phys_to_bus((u32)&txb[0]));
+	tx_ring[0].next = cpu_to_le32(phys_to_bus((u32)&tx_ring[1]));
+
+	/* this descriptor should never get used, since it will never be owned
+	   by the machine (status will always == 0) */
 
-	rxRingSize = NUM_RX_DESC;
-	txRingSize = NUM_TX_DESC;
+	tx_ring[1].status = 0;
+	tx_ring[1].des1 = 0;
+	tx_ring[1].buf = cpu_to_le32(phys_to_bus((u32)&txb[0]));
+	tx_ring[1].next = cpu_to_le32(phys_to_bus((u32)&tx_ring[0]));
 
 	/* Write the end of list marker to the descriptor lists. */
-	rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
-	tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
+	tx_ring[1].des1 |= cpu_to_le32(TD_TER);
 
 	/* Tell the adapter where the TX/RX rings are located. */
-	OUTL(dev, phys_to_bus((u32) &rx_ring), DE4X5_RRBA);
-	OUTL(dev, phys_to_bus((u32) &tx_ring), DE4X5_TRBA);
+	OUTL(dev, phys_to_bus((u32) &rx_ring[0]), DE4X5_RRBA);
+	OUTL(dev, phys_to_bus((u32) &tx_ring[0]), DE4X5_TRBA);
+
+	if (chip_idx == COMET) {
+		/* Bit 18 (0x00040000) is reserved in the AN983B */
+		/* datasheet, but it is used by the tulip driver */
+		OUTL(dev, (INL(dev, (DE4X5_OMR)) & ~(OMR_PMS | OMR_PM)) | OMR_PS, DE4X5_OMR);
+		/* Enable automatic Tx underrun recovery */
+		OUTL(dev, INL(dev, 0x88) | 1, 0x88);
+//		OUTL(dev, INL(dev, 0x88) | 0x19, 0x88);
+	}
 
 	START_DE4X5(dev);
 
-	tx_new = 0;
-	rx_new = 0;
+	/* Start receiving */
+	OUTL(dev, POLL_DEMAND, DE4X5_RPD);
 
-	send_setup_frame(dev, bis);
+	if (chip_idx != COMET) {	/* No setup frame needed by COMET */
+		send_setup_frame(dev, bis);
+	}
 
 	return 1;
 }

@@ -389,90 +448,96 @@ static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int lengt
 {
 	int		status = -1;
 	int		i;
+	u32		len = length;
 
 	if (length <= 0) {
 		printf("%s: bad packet size: %d\n", dev->name, length);
 		goto Done;
 	}
 
-	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
+	for(i = 0; tx_ring[0].status & cpu_to_le32(T_OWN); i++) {
 		if (i >= TOUT_LOOP) {
-			printf("%s: tx error buffer not ready\n", dev->name);
+			printf(".%s: Tx not ready\n", dev->name);
 			goto Done;
 		}
 	}
 
-	tx_ring[tx_new].buf    = cpu_to_le32(phys_to_bus((u32) packet));
-	tx_ring[tx_new].des1   = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
-	tx_ring[tx_new].status = cpu_to_le32(T_OWN);
+	/* Disable the TX */
+	OUTL(dev, INL(dev, DE4X5_OMR) & ~OMR_ST, DE4X5_OMR);
+
+	memcpy(txb, (char*)packet, length);
+
+	/* setup the transmit descriptor */
+	tx_ring[0].des1 = cpu_to_le32(TD_LS | TD_FS | length);
+	tx_ring[0].status = cpu_to_le32(T_OWN);
 
+	/* Point to transmit descriptor */
+	OUTL(dev, phys_to_bus((u32) &tx_ring[0]), DE4X5_TRBA);
+
+	/* Enable the TX */
+	OUTL(dev, INL(dev, DE4X5_OMR) | OMR_ST, DE4X5_OMR);
+
+	/* Immediate transmit demand */
 	OUTL(dev, POLL_DEMAND, DE4X5_TPD);
 
-	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
+	for(i = 0; tx_ring[0].status & cpu_to_le32(T_OWN); i++) {
 		if (i >= TOUT_LOOP) {
-			printf(".%s: tx buffer not ready\n", dev->name);
+			printf(".%s: Tx Timeout\n", dev->name);
 			goto Done;
 		}
 	}
 
-	if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) {
+	if (le32_to_cpu(tx_ring[0].status) & TD_ES) {
 #if 0 /* test-only */
 		printf("TX error status = 0x%08X\n",
-			le32_to_cpu(tx_ring[tx_new].status));
+			le32_to_cpu(tx_ring[0].status));
 #endif
-		tx_ring[tx_new].status = 0x0;
+		tx_ring[0].status = 0x0;
 		goto Done;
 	}
 
 	status = length;
 
  Done:
-    tx_new = (tx_new+1) % NUM_TX_DESC;
 	return status;
 }
 
 static int dc21x4x_recv(struct eth_device* dev)
 {
-	s32		status;
+	u32		status;
+	int		rx_prv;
 	int		length    = 0;
 
-	for ( ; ; ) {
-		status = (s32)le32_to_cpu(rx_ring[rx_new].status);
+	status = (u32)le32_to_cpu(rx_ring[rx_new].status);
+	if (status & R_OWN)
+		return 0;
 
-		if (status & R_OWN) {
-			break;
-		}
+	if (status & RD_LS) {
+		/* Valid frame status */
+		if (status & RD_ES) {
+			/* There was an error */
+			printf("RX error status = 0x%08X\n", status);
+			rx_ring[rx_new].status = cpu_to_le32(R_OWN);
+		} else {
+			/* Received valid frame */
+			length = (int)(le32_to_cpu(rx_ring[rx_new].status) >> 16);
 
-		if (status & RD_LS) {
-			/* Valid frame status.
-			 */
-			if (status & RD_ES) {
-
-				/* There was an error.
-				 */
-				printf("RX error status = 0x%08X\n", status);
-			} else {
-				/* A valid frame received.
-				 */
-				length = (le32_to_cpu(rx_ring[rx_new].status) >> 16);
-
-				/* Pass the packet up to the protocol
-				 * layers.
-				 */
-				NetReceive(NetRxPackets[rx_new], length - 4);
-			}
+			/* Pass the packet up to the protocol layers. */
+			unsigned char rxdata[BUFLEN];
+			memcpy(rxdata, rxb + rx_new * BUFLEN, length - 4);
 
-			/* Change buffer ownership for this frame, back
-			 * to the adapter.
-			 */
+			/* Give buffer ownership for this
+			 * frame back to the adapter */
 			rx_ring[rx_new].status = cpu_to_le32(R_OWN);
-		}
 
-		/* Update entry information.
-		 */
-		rx_new = (rx_new + 1) % rxRingSize;
+			/* Pass the received packet to the upper layer */
+			NetReceive(rxdata, length - 4);
+		}
 	}
 
+	/* Update current descriptor index */
+	rx_new = (rx_new + 1) % NUM_RX_DESC;
+
 	return length;
 }
 

@@ -483,7 +548,6 @@ static void dc21x4x_halt(struct eth_device* dev)
 	STOP_DE4X5(dev);
 	OUTL(dev, 0, DE4X5_SICR);
 
-	pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP);
 }
 
 static void send_setup_frame(struct eth_device* dev, bd_t *bis)

@@ -501,30 +565,29 @@ static void send_setup_frame(struct eth_device* dev, bd_t *bis)
 		}
 	}
 
-	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
+	for(i = 0; tx_ring[0].status & cpu_to_le32(T_OWN); i++) {
 		if (i >= TOUT_LOOP) {
 			printf("%s: tx error buffer not ready\n", dev->name);
 			goto Done;
 		}
 	}
 
-	tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0]));
-	tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN);
-	tx_ring[tx_new].status = cpu_to_le32(T_OWN);
+	tx_ring[0].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0]));
+	tx_ring[0].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN);
+	tx_ring[0].status = cpu_to_le32(T_OWN);
 
 	OUTL(dev, POLL_DEMAND, DE4X5_TPD);
 
-	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
+	for(i = 0; tx_ring[0].status & cpu_to_le32(T_OWN); i++) {
 		if (i >= TOUT_LOOP) {
 			printf("%s: tx buffer not ready\n", dev->name);
 			goto Done;
 		}
 	}
 
-	if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {
-		printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status));
+	if (le32_to_cpu(tx_ring[0].status) != 0x7FFFFFFF) {
+		printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[0].status));
 	}
-	tx_new = (tx_new+1) % NUM_TX_DESC;
 
 Done:
 	return;

@@ -543,7 +606,7 @@ sendto_srom(struct eth_device* dev, u_int command, u_long addr)
 static int
 getfrom_srom(struct eth_device* dev, u_long addr)
 {
-	s32 tmp;
+	u32 tmp;
 
 	tmp = INL(dev, addr);
 	udelay(1);

@@ -708,19 +771,27 @@ static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_
 #ifndef CONFIG_TULIP_FIX_DAVICOM
 static void read_hw_addr(struct eth_device *dev, bd_t *bis)
 {
-	u_short tmp, *p = (u_short *)(&dev->enetaddr[0]);
-	int i, j = 0;
-
-	for (i = 0; i < (ETH_ALEN >> 1); i++) {
-		tmp = read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1) + i));
-		*p = le16_to_cpu(tmp);
-		j += *p++;
-	}
+	if (chip_idx == COMET) {
+		/* COMET reads the ehernet address directly from the EEPROM */
+		*(u32 *)dev->enetaddr = cpu_to_le32(INL(dev, 0xA4));
+		*(u16 *)(dev->enetaddr+4) = cpu_to_le16(INL(dev, 0xA8));
+		*(u32 *)bis->bi_enetaddr = *(u32 *)dev->enetaddr;
+		*(u16 *)(bis->bi_enetaddr+4) = *(u16 *)(dev->enetaddr+4);
+	} else {
+		u_short tmp, *p = (u_short *)(&dev->enetaddr[0]);
+		int i, j = 0;
+
+		for (i = 0; i < (ETH_ALEN >> 1); i++) {
+			tmp=read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1)+i));
+			*p = le16_to_cpu(tmp);
+			j += *p++;
+		}
 
-	if ((j == 0) || (j == 0x2fffd)) {
-		memset (dev->enetaddr, 0, ETH_ALEN);
-		debug ("Warning: can't read HW address from SROM.\n");
-		goto Done;
+		if ((j == 0) || (j == 0x2fffd)) {
+			memset (dev->enetaddr, 0, ETH_ALEN);
+			debug ("Warning: can't read HW address from SROM.\n");
+			goto Done;
+		}
 	}
 
 	return;

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new file mode 100644
index 0000000..c59be16
@@ -0,0 +1,509 @@
+/*
+ * Copyright (C) 2006 Mihai Georgian <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if 0
+#define DEBUG
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
+
+/*-----------------------------------------------------------------------
+ * User configurable settings:
+ *   Mandatory settings:
+ *     CONFIG_IPADDR_LS		- the IP address of the LinkStation
+ *     CONFIG_SERVERIP_LS	- the address of the server for NFS/TFTP/DHCP/BOOTP
+ *   Optional settins:
+ *     CONFIG_NCIP_LS		- the adress of the computer running net console
+ *							  if not configured, it will be set to
+ *							  CONFIG_SERVERIP_LS
+ */
+
+
+#define CONFIG_IPADDR_LS	192.168.11.150
+#define CONFIG_SERVERIP_LS	192.168.11.149
+
+#if !defined(CONFIG_IPADDR_LS) || !defined(CONFIG_SERVERIP_LS)
+#error Both CONFIG_IPADDR_LS and CONFIG_SERVERIP_LS must be defined
+#endif
+
+#if !defined(CONFIG_NCIP_LS)
+#define CONFIG_NCIP_LS		CONFIG_SERVERIP_LS
+#endif
+
+/*----------------------------------------------------------------------
+ * DO NOT CHANGE ANYTHING BELOW, UNLESS YOU KNOW WHAT YOU ARE DOING
+ *---------------------------------------------------------------------*/
+
+#define CONFIG_MPC8245		1
+#define CONFIG_LINKSTATION	1
+
+/*---------------------------------------
+ * Supported models
+ *
+ * LinkStation HDLAN /KuroBox Standard (CONFIG_HLAN)
+ * LinkStation old model               (CONFIG_LAN) - totally untested
+ * LinkStation HGLAN / KuroBox HG      (CONFIG_HGLAN)
+ *
+ * Models not supported yet
+ * TeraStatin                          (CONFIG_HTGL)
+ */
+
+#if defined(CONFIG_HLAN) || defined(CONFIG_LAN)
+#define CONFIG_IDENT_STRING		" LinkStation / KuroBox"
+#elif defined(CONFIG_HGLAN)
+#define CONFIG_IDENT_STRING		" LinkStation HG / KuroBox HG"
+#elif defined(CONFIG_HTGL)
+#define CONFIG_IDENT_STRING		" TeraStation"
+#else
+#error No LinkStation model defined
+#endif
+
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#undef CONFIG_BOOT_RETRY_TIME
+
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT		"Boot in %02d seconds ('s' to stop)..."
+#define CONFIG_AUTOBOOT_STOP_STR	"s"
+
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EXT2
+
+#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_ALL
+
+#define CONFIG_OF_FLAT_TREE	1
+
+#ifdef CONFIG_OF_FLAT_TREE
+#define OF_CPU			"PowerPC,603e"
+#define OF_SOC			"soc10x at 80000000"
+#define OF_STDOUT_PATH		"/soc10x/serial at 80004600"
+#endif
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <config_cmd_default.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP				/* undef to save memory		*/
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_MAXARGS		16		/* Max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR		0x00800000	/* Default load address: 8 MB	*/
+
+#define CONFIG_BOOTCOMMAND  	"run bootcmd1"
+#define CONFIG_BOOTARGS		"root=/dev/sda1 console=ttyS1,57600 [email protected]/eth0, at 192.168.1.1/00:50:BF:A4:59:71 rtc-rs5c372.probe=0,0x32 debug"
+#define CONFIG_NFSBOOTCOMMAND  	"bootp;run nfsargs;bootm"
+
+#define CFG_CONSOLE_IS_IN_ENV
+
+#define XMK_STR(x)		#x
+#define MK_STR(x)		XMK_STR(x)
+
+#if defined(CONFIG_HLAN) || defined(CONFIG_LAN)
+#define UBFILE			"share/u-boot/u-boot-hd.flash.bin"
+#elif defined(CONFIG_HGLAN)
+#define UBFILE			"share/u-boot/u-boot-hg.flash.bin"
+#elif defined(CONFIG_HTGL)
+#define UBFILE			"share/u-boot/u-boot-ht.flash.bin"
+#else
+#error No LinkStation model defined
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS						\
+	"autoload=no\0"								\
+	"stdin=nc\0"								\
+	"stdout=nc\0"								\
+	"stderr=nc\0"								\
+	"ipaddr="MK_STR(CONFIG_IPADDR_LS)"\0"					\
+	"netmask=255.255.255.0\0"						\
+	"serverip="MK_STR(CONFIG_SERVERIP_LS)"\0"				\
+	"ncip="MK_STR(CONFIG_NCIP_LS)"\0"					\
+	"netretry=no\0"								\
+	"nc=setenv stdin nc;setenv stdout nc;setenv stderr nc\0"		\
+	"ser=setenv stdin serial;setenv stdout serial;setenv stderr serial\0"	\
+	"ldaddr=800000\0"							\
+	"hdpart=0:1\0"								\
+	"hdfile=boot/uImage\0"							\
+	"hdload=echo Loading ${hdpart}:${hdfile};ext2load ide ${hdpart} ${ldaddr} ${hdfile};ext2load ide ${hdpart} 7f0000 boot/kuroboxHG.dtb\0"	\
+	"boothd=setenv bootargs " CONFIG_BOOTARGS ";bootm ${ldaddr} - 7f0000\0"	\
+	"hdboot=run hdload;run boothd\0"					\
+	"flboot=setenv bootargs root=/dev/hda1;bootm ffc00000\0"		\
+	"emboot=setenv bootargs root=/dev/ram0;bootm ffc00000\0"		\
+	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0"	\
+	"bootretry=30\0"							\
+	"bootcmd1=run hdboot;run flboot\0"					\
+	"bootcmd2=run flboot\0"							\
+	"bootcmd3=run emboot\0"							\
+	"writeng=protect off fff70000 fff7ffff;era fff70000 fff7ffff;mw.l 800000 4e474e47 1;cp.b 800000 fff70000 4\0" \
+	"writeok=protect off fff70000 fff7ffff;era fff70000 fff7ffff;mw.l 800000 4f4b4f4b 1;cp.b 800000 fff70000 4\0" \
+	"ubpart=0:3\0"								\
+	"ubfile="UBFILE"\0"							\
+	"ubload=echo Loading ${ubpart}:${ubfile};ext2load ide ${ubpart} ${ldaddr} ${ubfile}\0" \
+	"ubsaddr=fff00000\0"							\
+	"ubeaddr=fff2ffff\0"							\
+	"ubflash=protect off ${ubsaddr} ${ubeaddr};era ${ubsaddr} ${ubeaddr};cp.b ${ldaddr} ${ubsaddr} ${filesize};cmp.b ${ldaddr} ${ubsaddr} ${filesize}\0" \
+	"upgrade=run ubload ubflash\0"
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ */
+#define CONFIG_PCI
+/* Verified: CONFIG_PCI_PNP doesn't work */
+#undef CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+
+#ifndef CONFIG_PCI_PNP
+/* Keep the following defines in sync with the BAT mappings */
+
+#define PCI_ETH_IOADDR      0xbfff00
+#define PCI_ETH_MEMADDR     0xbffffc00
+#define PCI_IDE_IOADDR      0xbffed0
+#define PCI_IDE_MEMADDR     0xbffffb00
+#define PCI_USB0_IOADDR     0
+#define PCI_USB0_MEMADDR    0xbfffe000
+#define PCI_USB1_IOADDR     0
+#define PCI_USB1_MEMADDR    0xbfffd000
+#define PCI_USB2_IOADDR     0
+#define PCI_USB2_MEMADDR    0xbfffcf00
+
+#endif
+
+/*-----------------------------------------------------------------------
+ * Ethernet stuff
+ */
+#define CONFIG_NET_MULTI
+
+#if defined(CONFIG_LAN) || defined(CONFIG_HLAN)
+#define CONFIG_TULIP
+#define CONFIG_TULIP_USE_IO
+#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL)
+#define CONFIG_RTL8169
+#endif
+
+#define CONFIG_NET_RETRY_COUNT		5
+
+#define CONFIG_NETCONSOLE
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE	    	0x00000000
+
+#define CFG_FLASH_BASE      	0xFFC00000
+#define CFG_FLASH_SIZE		0x00400000
+#define CFG_MONITOR_BASE    	TEXT_BASE
+
+#define CFG_RESET_ADDRESS   	0xFFF00100
+#define CFG_EUMB_ADDR	    	0x80000000
+#define CFG_PCI_MEM_ADDR	0xB0000000
+#define CFG_MISC_REGION_ADDR	0xFE000000
+
+#define CFG_MONITOR_LEN     	0x00040000	/* 256 kB			*/
+#define CFG_MALLOC_LEN      	(512 << 10)	/* Reserve some kB for malloc()	*/
+
+#define CFG_MEMTEST_START   	0x00100000	/* memtest works on		*/
+#define CFG_MEMTEST_END	    	0x00800000	/* 1M ... 8M in DRAM		*/
+
+/* Maximum amount of RAM */
+#if defined(CONFIG_HLAN) || defined(CONFIG_LAN)
+#define CFG_MAX_RAM_SIZE    	0x04000000	/* 64MB of SDRAM  */
+#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL)
+#define CFG_MAX_RAM_SIZE    	0x08000000	/* 128MB of SDRAM */
+#else
+#error Unknown LinkStation type
+#endif
+
+/*-----------------------------------------------------------------------
+ * Change TEXT_BASE in bord/linkstation/config.mk to get a RAM build
+ *
+ * RAM based builds are for testing purposes. A Linux module, uloader.o,
+ * exists to load U-Boot and pass control to it
+ *
+ * Always do "make clean" after changing the build type
+ */
+#if CFG_MONITOR_BASE < CFG_FLASH_BASE
+#define CFG_RAMBOOT
+#endif
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+#if 1 /* RAM is available when the first C function is called */
+#define CFG_INIT_RAM_ADDR	(CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE - 0x1000)
+#else
+#define CFG_INIT_RAM_ADDR	0x40000000
+#endif
+#define CFG_INIT_RAM_END	0x1000
+#define CFG_GBL_DATA_SIZE	128
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+/*----------------------------------------------------------------------
+ * Serial configuration
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		57600
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+
+#define CFG_NS16550_REG_SIZE	1
+
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_NS16550_COM1	(CFG_EUMB_ADDR + 0x4600)	/* Console port	*/
+#define CFG_NS16550_COM2	(CFG_EUMB_ADDR + 0x4500)	/* AVR port	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * For the detail description refer to the MPC8245 user's manual.
+ *
+ * Unless indicated otherwise, the values are
+ * taken from the orignal Linkstation boot code
+ *
+ * Most of the low level configuration setttings are normally used
+ * in cpu/mpc824x/cpu_init.c which is NOT used by this implementation.
+ * Low level initialisation is done in board/linkstation/early_init.S
+ * The values below are included for reference purpose only
+ */
+
+/* FIXME: 32.768 MHz is the crystal frequency but */
+/* the real frequency is lower by about 0.75%     */
+#define CONFIG_SYS_CLK_FREQ	32768000
+#define CFG_HZ			1000
+
+/* Bit-field values for MCCR1.  */
+#define CFG_ROMNAL      0
+#define CFG_ROMFAL      11
+
+#define CFG_BANK0_ROW	2       /* Only bank 0 used: 13 x n x 4 */
+#define CFG_BANK1_ROW	0
+#define CFG_BANK2_ROW	0
+#define CFG_BANK3_ROW	0
+#define CFG_BANK4_ROW	0
+#define CFG_BANK5_ROW	0
+#define CFG_BANK6_ROW	0
+#define CFG_BANK7_ROW	0
+
+/* Bit-field values for MCCR2.  */
+#define CFG_TSWAIT      0
+#if defined(CONFIG_LAN) || defined(CONFIG_HLAN)
+#define CFG_REFINT      0x15e0
+#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL)
+#define CFG_REFINT      0x1580
+#endif
+
+/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
+#define CFG_BSTOPRE	0x91c
+
+/* Bit-field values for MCCR3.  */
+#define CFG_REFREC      7
+
+/* Bit-field values for MCCR4.  */
+#define CFG_PRETOACT		2
+#define CFG_ACTTOPRE		2	/* Original value was 2	*/
+#define CFG_ACTORW		2
+#if defined(CONFIG_LAN) || defined(CONFIG_HLAN)
+#define CFG_SDMODE_CAS_LAT	2	/* For 100MHz bus	*/
+//#define CFG_SDMODE_BURSTLEN	3
+#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL)
+#define CFG_SDMODE_CAS_LAT	3	/* For 133MHz bus	*/
+//#define CFG_SDMODE_BURSTLEN	2
+#endif
+#define CFG_REGISTERD_TYPE_BUFFER 1
+#define CFG_EXTROM		1	/* Original setting but there is no EXTROM */
+#define CFG_REGDIMM		0
+#define CFG_DBUS_SIZE2		1
+#define CFG_SDMODE_WRAP		0
+
+#define CFG_PGMAX		0x32	/* All boards use this setting. Original 0x92 */
+#define CFG_SDRAM_DSCD		0x30
+
+/* Memory bank settings.
+ * Only bits 20-29 are actually used from these vales to set the
+ * start/end addresses. The upper two bits will always be 0, and the lower
+ * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
+ * address. Refer to the MPC8240 book.
+ */
+
+#define CFG_BANK0_START	    0x00000000
+#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
+#define CFG_BANK0_ENABLE    1
+#define CFG_BANK1_START     0x3ff00000
+#define CFG_BANK1_END       0x3fffffff
+#define CFG_BANK1_ENABLE    0
+#define CFG_BANK2_START     0x3ff00000
+#define CFG_BANK2_END       0x3fffffff
+#define CFG_BANK2_ENABLE    0
+#define CFG_BANK3_START     0x3ff00000
+#define CFG_BANK3_END       0x3fffffff
+#define CFG_BANK3_ENABLE    0
+#define CFG_BANK4_START     0x3ff00000
+#define CFG_BANK4_END       0x3fffffff
+#define CFG_BANK4_ENABLE    0
+#define CFG_BANK5_START     0x3ff00000
+#define CFG_BANK5_END       0x3fffffff
+#define CFG_BANK5_ENABLE    0
+#define CFG_BANK6_START     0x3ff00000
+#define CFG_BANK6_END       0x3fffffff
+#define CFG_BANK6_ENABLE    0
+#define CFG_BANK7_START     0x3ff00000
+#define CFG_BANK7_END       0x3fffffff
+#define CFG_BANK7_ENABLE    0
+
+#define CFG_ODCR	    0x15
+
+/*----------------------------------------------------------------------
+ * Initial BAT mappings
+ */
+
+/* NOTES:
+ * 1) GUARDED and WRITETHROUGH not allowed in IBATS
+ * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
+ */
+
+/* SDRAM */
+#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L	CFG_IBAT0L
+#define CFG_DBAT0U	CFG_IBAT0U
+
+/* EUMB: 1MB of address space */
+#define CFG_IBAT1L	(CFG_EUMB_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT1U	(CFG_EUMB_ADDR | BATU_BL_1M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT1L	(CFG_IBAT1L | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT1U	CFG_IBAT1U
+
+/* PCI Mem: 256MB of address space */
+#define CFG_IBAT2L	(CFG_PCI_MEM_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U	(CFG_PCI_MEM_ADDR | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT2L	(CFG_IBAT2L | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT2U	CFG_IBAT2U
+
+/* PCI and local ROM/Flash: last 32MB of address space */
+#define CFG_IBAT3L	(CFG_MISC_REGION_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U	(CFG_MISC_REGION_ADDR | BATU_BL_32M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT3L	(CFG_IBAT3L | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT3U	CFG_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ *
+ * FIXME: This doesn't appear to be true for the newer kernels
+ * which map more that 8 MB
+ */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI			/* The flash is CFI compatible	*/
+#define CFG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
+
+#undef  CFG_FLASH_PROTECTION
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
+#define CFG_MAX_FLASH_SECT	72	/* Max number of sectors per flash	*/
+
+#define CFG_FLASH_ERASE_TOUT	12000
+#define CFG_FLASH_WRITE_TOUT	1000
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
+
+#define CFG_ENV_IS_IN_FLASH
+/*
+ * The original LinkStation flash organisation uses
+ * 448 kB (0xFFF00000 - 0xFFF6FFFF) for the boot loader
+ * We use the last sector of this area to store the environment
+ * which leaves max. 384 kB for the U-Boot itself
+ */
+#define CFG_ENV_ADDR		0xFFF60000
+#define CFG_ENV_SIZE		0x00010000
+#define CFG_ENV_SECT_SIZE	0x00010000
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32
+#ifdef CONFIG_CMD_KGDB
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA definitions
+ */
+#undef  CONFIG_IDE_LED				/* No IDE LED			*/
+#define CONFIG_IDE_RESET			/* no reset for ide supported	*/
+#define CONFIG_IDE_PREINIT			/* check for units		*/
+#define CONFIG_LBA48				/* 48 bit LBA supported		*/
+
+#if defined(CONFIG_LAN) || defined(CONFIG_HLAN) || defined(CONFIG_HGLAN)
+#define CFG_IDE_MAXBUS		1		/* Scan only 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1		/* Only 1 drive per IDE bus	*/
+#elif defined(CONFIG_HGTL)
+#define CFG_IDE_MAXBUS		2		/* Max. 2 IDE busses		*/
+#define CFG_IDE_MAXDEVICE	2		/* max. 2 drives per IDE bus	*/
+#else
+#error Config IDE: Unknown LinkStation type
+#endif
+
+#define CFG_ATA_BASE_ADDR	0
+
+#define CFG_ATA_DATA_OFFSET	0		/* Offset for data I/O		*/
+#define CFG_ATA_REG_OFFSET	0		/* Offset for normal registers	*/
+#define CFG_ATA_ALT_OFFSET	0		/* Offset for alternate registers */
+
+/*-----------------------------------------------------------------------
+ * Partitions and file system
+ */
+#define CONFIG_DOS_PARTITION
+
+/*-----------------------------------------------------------------------
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+#endif	/* __CONFIG_H */